Local area network design. - Andrew Hopper; Steve Temple; Robin Williamson (Addison-Wesley, 1986)

The Design and Evaluation of an Asynchronous Microprocessor. - Stephen B. Furber; Paul Day; Jim D. Garside; N. C. Paver; Steve Temple; John V. Woods (ICCD, 1994)

The AMULET2e cache system. - Jim D. Garside; Steve Temple; Rahul Mehra (ASYNC, 1996)

AMULET2e: An Asynchronous Embedded Controller. - Stephen B. Furber; Jim D. Garside; Steve Temple; Jianwei Liu; Paul Day; N. C. Paver (ASYNC, 1997)

AMULET1: A Asynchronous ARM Microprocessor. - John V. Woods; Paul Day; Stephen B. Furber; Jim D. Garside; N. C. Paver; Steve Temple (IEEE Trans. Computers, 1997)

Asynchronous Embedded Control. - Stephen B. Furber; Jim D. Garside; Steve Temple; Paul Day; Nigel C. Paver (Integr. Comput. Aided Eng., 1998)

AMULET2e: an asynchronous embedded controller. - Stephen B. Furber; James Garside; Peter A. Riocreux; Steve Temple; Paul Day; Jianwei Liu; Nigel C. Paver (Proc. IEEE, 1999)

AMULET3i - An Asynchronous System-on-Chip. - Jim D. Garside; W. J. Bainbridge; Andrew Bardsley; David M. Clark; David A. Edwards; Stephen B. Furber; David W. Lloyd; Siamak Mohammadi; J. S. Pepper; Steve Temple; John V. Woods; Jianwei Liu; et al. (ASYNC, 2000)

Power Management in the Amulet Microprocessors. - Stephen B. Furber; Aristides Efthymiou; Jim D. Garside; David W. Lloyd; Mike J. G. Lewis; Steve Temple (IEEE Des. Test Comput., 2001)

SPA - A Synthesisable Amulet Core for Smartcard pplications. - W. J. Bainbridge; Andrew Bardsley; Steve Temple; Jim D. Garside; Peter A. Riocreux; Luis A. Plana (ASYNC, 2002)

SPA - a secure Amulet core for smartcard applications. - Luis A. Plana; Peter A. Riocreux; W. J. Bainbridge; Andrew Bardsley; Steve Temple; Jim D. Garside; Z. C. Yu (Microprocess. Microsystems, 2003)

Sparse distributed memory using N-of-M codes. - Stephen B. Furber; John Bainbridge; J. Mike Cumpstey; Steve Temple (Neural Networks, 2004)

On-chip and inter-chip networks for modeling large-scale neural systems. - Stephen B. Furber; Steve Temple; Andrew D. Brown (ISCAS, 2006)

A GALS Infrastructure for a Massively Parallel Multiprocessor. - Luis A. Plana; Stephen B. Furber; Steve Temple; Muhammad Mukaram Khan; Yebin Shi; Jian Wu; Shufan Yang (IEEE Des. Test Comput., 2007)

Neural Systems Engineering. - Steve B. Furber; Steve Temple (Computational Intelligence: A Compendium, 2008)

The Amulet chips: Architectural development for asynchronous microprocessors. - Jim D. Garside; Stephen B. Furber; Steve Temple; Viv Woods (ICECS, 2009)

Algorithm and software for simulation of spiking neural networks on the multi-chip SpiNNaker system. - Xin Jin 003; Francesco Galluppi; Cameron Patterson; Alexander D. Rast; Sergio Davies; Steve Temple; Steve B. Furber (IJCNN, 2010)

Modeling Spiking Neural Networks on SpiNNaker. - Xin Jin 003; Mikel Luján; Luis A. Plana; Sergio Davies; Steve Temple; Steve B. Furber (Comput. Sci. Eng., 2010)

SpiNNaker: Design and Implementation of a GALS Multicore System-on-Chip. - Luis A. Plana; David M. Clark; Simon Davidson; Steve B. Furber; Jim D. Garside; Eustace Painkras; Jeffrey Pepper; Steve Temple; John Bainbridge (ACM J. Emerg. Technol. Comput. Syst., 2011)

Event-driven configuration of a neural network CMP system over an homogeneous interconnect fabric. - Mukaram M. Khan; Alexander D. Rast; Javier Navaridas; X. Jin; Luis A. Plana; Mikel Luján; Steve Temple; Cameron Patterson; Dominic Richards; John V. Woods; José Miguel-Alonso; Stephen B. Furber (Parallel Comput., 2011)

An Asynchronous Fully Digital Delay Locked Loop for DDR SDRAM Data Recovery. - Jim D. Garside; Stephen B. Furber; Steve Temple; David M. Clark; Luis A. Plana (ASYNC, 2012)

SpiNNaker: A multi-core System-on-Chip for massively-parallel neural net simulation. - Eustace Painkras; Luis A. Plana; Jim D. Garside; Steve Temple; Simon Davidson; Jeffrey Pepper; David M. Clark; Cameron Patterson; Steve B. Furber (CICC, 2012)

Scalable communications for a million-core neural processing architecture. - Cameron Patterson; Jim D. Garside; Eustace Painkras; Steve Temple; Luis A. Plana; Javier Navaridas; Thomas Sharp; Steve B. Furber (J. Parallel Distributed Comput., 2012)

A location-independent direct link neuromorphic interface. - Alexander D. Rast; Johannes Partzsch; Christian Mayr 001; Johannes Schemmel; Stefan Hartmann; Luis A. Plana; Steve Temple; David R. Lester; René Schüffny; Steve B. Furber (IJCNN, 2013)

SpiNNaker: A 1-W 18-Core System-on-Chip for Massively-Parallel Neural Network Simulation. - Eustace Painkras; Luis A. Plana; Jim D. Garside; Steve Temple; Francesco Galluppi; Cameron Patterson; David R. Lester; Andrew D. Brown; Steve B. Furber (IEEE J. Solid State Circuits, 2013)

SpiNNaker: Fault tolerance in a power- and area- constrained large-scale neuromimetic architecture. - Javier Navaridas; Steve B. Furber; Jim D. Garside; Xin Jin 003; Mukaram M. Khan; David R. Lester; Mikel Luján; José Miguel-Alonso; Eustace Painkras; Cameron Patterson; Luis A. Plana; Alexander D. Rast; et al. (Parallel Comput., 2013)

Overview of the SpiNNaker System Architecture. - Steve B. Furber; David R. Lester; Luis A. Plana; Jim D. Garside; Eustace Painkras; Steve Temple; Andrew D. Brown (IEEE Trans. Computers, 2013)

On generating multicast routes for SpiNNaker. - Javier Navaridas; Mikel Luján; Luis A. Plana; Steve Temple; Steve B. Furber (Conf. Computing Frontiers, 2014)

The SpiNNaker Project. - Steve B. Furber; Francesco Galluppi; Steve Temple; Luis A. Plana (Proc. IEEE, 2014)

SpiNNaker: Enhanced multicast routing. - Javier Navaridas; Mikel Luján; Luis A. Plana; Steve Temple; Steve B. Furber (Parallel Comput., 2015)

SpiNNaker - Programming Model. - Andrew D. Brown; Stephen B. Furber; Jeffrey S. Reeve; Jim D. Garside; Kier J. Dugan; Luis A. Plana; Steve Temple (IEEE Trans. Computers, 2015)

Fast Predictive Handshaking in Synchronous FPGAs for Fully Asynchronous Multisymbol Chip Links: Application to SpiNNaker 2-of-7 Links. - Amirreza Yousefzadeh; Luis A. Plana; Steve Temple; Teresa Serrano-Gotarredona; Steve B. Furber; Bernabé Linares-Barranco (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

Parallel distribution of an inner hair cell and auditory nerve model for real-time application. - Robert James; Jim D. Garside; Michael Hopkins; Luis A. Plana; Steve Temple; Simon Davidson; Steve B. Furber (BioCAS, 2017)

Live demonstration: Dynamic voltage and frequency scaling for neuromorphic many-core systems. - Sebastian Höppner; Yexin Yan; Bernhard Vogginger; Andreas Dixius; Johannes Partzsch; Prateek Joshi; Felix Neumärker; Stephan Hartmann 002; Stefan Schiefer; Stefan Scholze; Georg Ellguth; Love Cederstroem; et al. (ISCAS, 2017)

Dynamic voltage and frequency scaling for neuromorphic many-core systems. - Sebastian Höppner; Yexin Yan; Bernhard Vogginger; Andreas Dixius; Johannes Partzsch; Felix Neumärker; Stephan Hartmann 002; Stefan Schiefer; Stefan Scholze; Georg Ellguth; Love Cederstroem; Matthias Eberlein; et al. (ISCAS, 2017)

On Multiple AER Handshaking Channels Over High-Speed Bit-Serial Bidirectional LVDS Links With Flow-Control and Clock-Correction on Commercial FPGAs for Scalable Neuromorphic Systems. - Amirreza Yousefzadeh; Miroslaw Jablonski; Taras Iakymchuk; Alejandro Linares-Barranco; Alfredo Rosado; Luis A. Plana; Steve Temple; Teresa Serrano-Gotarredona; Steve B. Furber; Bernabé Linares-Barranco (IEEE Trans. Biomed. Circuits Syst., 2017)

spiNNlink: FPGA-Based Interconnect for the Million-Core SpiNNaker System. - Luis A. Plana; Jim D. Garside; Jonathan Heathcote; Jeffrey Pepper; Steve Temple; Simon Davidson; Mikel Luján; Steve B. Furber (IEEE Access, 2020)