The design methodology and implementation of a first-generation CELL processor: a multi-core SoC. - Dac C. Pham; Erwin Behnen; Mark Bolliger; H. Peter Hofstee; Charles R. Johns; James A. Kahle; Atsushi Kameyama; John M. Keaty; Bob Le; Yoshio Masubuchi; Stephen D. Posluszny; Mack W. Riley; et al. (CICC, 2005)

Cell Processor Low-Power Design Methodology. - Daniel L. Stasiak; Rajat Chaudhry; Dennis Cox; Stephen D. Posluszny; James D. Warnock; Steve Weitzel; Dieter F. Wendel; Michael Wang 001 (IEEE Micro, 2005)

Key features of the design methodology enabling a multi-core SoC implementation of a first-generation CELL processor. - Dac C. Pham; Hans-Werner Anderson; Erwin Behnen; Mark Bolliger; Sanjay Gupta; H. Peter Hofstee; Paul E. Harvey; Charles R. Johns; James A. Kahle; Atsushi Kameyama; John M. Keaty; Bob Le; et al. (ASP-DAC, 2006)

Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor. - Dac C. Pham; Tony Aipperspach; David Boerstler; Mark Bolliger; Rajat Chaudhry; Dennis Cox; Paul E. Harvey; H. Peter Hofstee; Charles R. Johns; Jim Kahle; Atsushi Kameyama; John M. Keaty; et al. (IEEE J. Solid State Circuits, 2006)

Implementation of the 65nm Cell Broadband Engine. - Mack W. Riley; Brian K. Flachs; Sang H. Dhong; Gilles Gervais; Steve Weitzel; Michael Wang 001; David Boerstler; Mark Bolliger; John M. Keaty; Jürgen Pille; R. Berry; Osamu Takahashi; et al. (CICC, 2007)

On-chip Timing Uncertainty Measurements on IBM Microprocessors. - Robert L. Franch; Phillip J. Restle; James K. Norman; William V. Huott; Joshua Friedrich; R. Dixon; Steve Weitzel; K. van Goor; Gerard Salem (ITC, 2008)

A Resonant Global Clock Distribution for the Cell Broadband Engine Processor. - Steven C. Chan; Phillip J. Restle; Thomas J. Bucelot; John S. Liberty; Stephen Weitzel; John M. Keaty; Brian K. Flachs; Richard Volant; Peter Kapusta; Jeffrey S. Zimmerman (IEEE J. Solid State Circuits, 2009)

The implementation of POWER7TM: A highly parallel and scalable multi-core high-end server processor. - Dieter F. Wendel; Ronald N. Kalla; Robert Cargnoni; Joachim G. Clabes; Joshua Friedrich; Roland Frech; James A. Kahle; Balaram Sinharoy; William J. Starke; Scott A. Taylor; Steve Weitzel; Sam G. Chu; et al. (ISSCC, 2010)

A 5.2GHz microprocessor chip for the IBM zEnterprise™ system. - James D. Warnock; Y. Chan; William V. Huott; Sean M. Carey; Michael F. Fee; Huajun Wen; Mary Jo Saccamango; Frank Malgioglio; Patrick J. Meaney; Donald W. Plass; Yuen H. Chan; Mark D. Mayo; et al. (ISSCC, 2011)

POWER7™, a Highly Parallel, Scalable Multi-Core High End Server Processor. - Dieter F. Wendel; Ronald N. Kalla; James D. Warnock; Robert Cargnoni; Sam G. Chu; Joachim G. Clabes; Daniel Dreps; David Hrusecky; Joshua Friedrich; Md. Saiful Islam 004; James A. Kahle; Jens Leenstra; et al. (IEEE J. Solid State Circuits, 2011)