A VLSI Implementation of a Cascade Viterbi Decoder with Traceback. - Gennady Feygin; Paul Chow; P. Glenn Gulak; John Chappel; Grant Goodes; Oswin Hall; Ahmad Sayes; Satwant Singh; Michael B. Smith; Steven J. E. Wilton (ISCAS, 1993)

Architectural Support for Block Transfers in a Shared-Memory Multiprocessor. - Steven J. E. Wilton; Zvonko G. Vranesic (SPDP, 1993)

Tradeoffs in Two-Level On-Chip Caching. - Norman P. Jouppi; Steven J. E. Wilton (ISCA, 1994)

Architecture of Centralized Field-Configurable Memory. - Steven J. E. Wilton; Jonathan Rose; Zvonko G. Vranesic (FPGA, 1995)

CACTI: an enhanced cache access and cycle time model. - Steven J. E. Wilton; Norman P. Jouppi (IEEE J. Solid State Circuits, 1996)

Memory-to-Memory Connection Structures in FPGAs with Embedded Memory Arrays. - Steven J. E. Wilton; Jonathan Rose; Zvonko G. Vranesic (FPGA, 1997)

Implementing logic in FPGA embedded memory arrays: architectural implications. - Steven J. E. Wilton (CICC, 1998)

SMAP: Heterogeneous Technology Mapping for Area Reduction in FPGAs with Embedded Memory Arrays. - Steven J. E. Wilton (FPGA, 1998)

Logical-to-Physical Memory Mapping for FPGAs with Dual-Port Embedded Arrays. - William K. C. Ho; Steven J. E. Wilton (FPL, 1999)

A New Switch Block for Segmented FPGAs. - M. Imran Masud; Steven J. E. Wilton (FPL, 1999)

The memory/logic interface in FPGAs with large embedded memory arrays. - Steven J. E. Wilton; Jonathan Rose; Zvonko G. Vranesic (IEEE Trans. Very Large Scale Integr. Syst., 1999)

Architecture of cluster-based FPGAs with memory. - Jason P. Clifford; Steven J. E. Wilton (CICC, 2000)

Heterogeneous technology mapping for FPGAs with dual-port embedded memory arrays. - Steven J. E. Wilton (FPGA, 2000)

FPGA Implementation of a Prototype WDM On-Line Scheduler. - Winnie W. Cheng; Steven J. E. Wilton; Babak Hamidzadeh (FPL, 2000)

Heterogeneous technology mapping for area reduction in FPGAs withembedded memory arrays. - Steven J. E. Wilton (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

Programmable logic IP cores in SoC design: opportunities and challenges. - Steven J. E. Wilton; Resve Saleh (CICC, 2001)

Detailed routing architectures for embedded programmable logic IP cores. - Peter Hallschmid; Steven J. E. Wilton (FPGA, 2001)

A crosstalk-aware timing-driven router for FPGAs. - Steven J. E. Wilton (FPGA, 2001)

Macrocell Architectures for Product Term Embedded Memory Arrays. - Ernie Lin; Steven J. E. Wilton (FPL, 2001)

Structural analysis and generation of synthetic digital circuits with memory. - Steven J. E. Wilton; Jonathan Rose; Zvonko G. Vranesic (IEEE Trans. Very Large Scale Integr. Syst., 2001)

The architecture of dual-mode FPGA embedded system blocks. - Ernie Lin; Steven J. E. Wilton (CICC, 2002)

On the sensitivity of FPGA architectural conclusions to experimental assumptions, tools, and techniques. - Andy Yan; Rebecca Cheng; Steven J. E. Wilton (FPGA, 2002)

A Flexible Power Model for FPGAs. - Kara K. W. Poon; Andy Yan; Steven J. E. Wilton (FPL, 2002)

Sensitivity of FPGA power evaluation. - Kara K. W. Poon; Steven J. E. Wilton (FPT, 2002)

Implementing logic in FPGA memory arrays: heterogeneous memory architectures. - Steven J. E. Wilton (FPT, 2002)

SoC implementation issues for synthesizable embedded programmable logic cores. - James C. H. Wu; Victor O. Aken'Ova; Steven J. E. Wilton; Resve A. Saleh (CICC, 2003)

Architectures and algorithms for synthesizable embedded programmable logic cores. - Noha Kafafi; Kimberly A. Bozman; Steven J. E. Wilton (FPGA, 2003)

Placement and routing for FPGA architectures supporting wide shallow memories. - Steven W. Oldridge; Steven J. E. Wilton (FPT, 2003)

On the Interaction Between Power-Aware FPGA CAD Algorithms. - Julien Lamoureux; Steven J. E. Wilton (ICCAD, 2003)

Sequential synthesizable embedded programmable logic cores for system-on-chip. - Andy Yan; Steven J. E. Wilton (CICC, 2004)

The Impact of Pipelining on Energy per Operation in Field-Programmable Gate Arrays. - Steven J. E. Wilton; Su-Shin Ang; Wayne Luk (FPL, 2004)

Interconnect architectures for modulo-scheduled coarse-grained reconfigurable arrays. - Steven J. E. Wilton; Noha Kafafi; Bingfeng Mei; Serge Vernalde (FPT, 2004)

Placement and routing for non-rectangular embedded programmable logic cores in SoC design. - Tony Wong; Steven J. E. Wilton (FPT, 2004)

An embedded flexible content-addressable memory core for inclusion in a Field-Programmable Gate Array. - Steven J. E. Wilton; Christopher W. Jones; Julien Lamoureux (ISCAS (2), 2004)

Advances in programmable logic. - Steven J. E. Wilton; Albert Stritter (CICC, 2005)

Register File Architecture Optimization in a Coarse-Grained Reconfigurable Architecture. - Zion S. Kwok; Steven J. E. Wilton (FCCM, 2005)

Dynamic Voltage Scaling for Commercial FPGAs. - Gary Chun Tak Chow; L. S. M. Tsui; Philip Heng Wai Leong; Wayne Luk; Steven J. E. Wilton (FPT, 2005)

Post-Silicon Debug Using Programmable Logic Cores. - Bradley R. Quinton; Steven J. E. Wilton (FPT, 2005)

Asynchronous IC Interconnect Network Design and Implementation Using a Standard ASIC Flow. - Bradley R. Quinton; Mark R. Greenstreet; Steven J. E. Wilton (ICCD, 2005)

Concentrator access networks for programmable logic cores on SoCs. - Bradley R. Quinton; Steven J. E. Wilton (ISCAS (1), 2005)

Challenges and opportunities for low power FPGAs in nanometer technologies. - Lei He 001; Mike Hutton; Tim Tuan; Steven J. E. Wilton (ISLPED, 2005)

On the Interaction between Power-Aware Computer-Aided Design Algorithms for Field-Programmable Gate Arrays. - Julien Lamoureux; Steven J. E. Wilton (J. Low Power Electron., 2005)

Design considerations for soft embedded programmable logic cores. - Steven J. E. Wilton; Noha Kafafi; James C. H. Wu; Kimberly A. Bozman; Victor O. Aken'Ova; Resve Saleh (IEEE J. Solid State Circuits, 2005)

A detailed power model for field-programmable gate arrays. - Kara K. W. Poon; Steven J. E. Wilton; Andy Yan (ACM Trans. Design Autom. Electr. Syst., 2005)

Routing architecture optimizations for high-density embedded programmable IP cores. - Peter Hallschmid; Steven J. E. Wilton (IEEE Trans. Very Large Scale Integr. Syst., 2005)

A novel FPGA architecture supporting wide, shallow memories. - Steven W. Oldridge; Steven J. E. Wilton (IEEE Trans. Very Large Scale Integr. Syst., 2005)

Virtual Embedded Blocks: A Methodology for Evaluating Embedded Elements in FPGAs. - Chun Hok Ho; Philip Heng Wai Leong; Wayne Luk; Steven J. E. Wilton; Sergio López-Buedo (FCCM, 2006)

FPGA clock network architecture: flexibility vs. area and power. - Julien Lamoureux; Steven J. E. Wilton (FPGA, 2006)

Power Implications of Implementing Logic Using FPGA Embedded Memory Arrays. - Scott Y. L. Chin; Clarence S. P. Lee; Steven J. E. Wilton (FPL, 2006)

Activity Estimation for Field-Programmable Gate Arrays. - Julien Lamoureux; Steven J. E. Wilton (FPL, 2006)

Architecture and CAD for FPGA Clock Networks. - Julien Lamoureux; Steven J. E. Wilton (FPL, 2006)

Activity-based power estimation and characterization of DSP and multiplier blocks in FPGAs. - Nathalie Chan King Choy; Steven J. E. Wilton (FPT, 2006)

System-on-Chip: Reuse and Integration. - Resve A. Saleh; Steven J. E. Wilton; Shahriar Mirabbasi; Alan J. Hu; Mark R. Greenstreet; Guy Lemieux; Partha Pratim Pande; Cristian Grecu; André Ivanov (Proc. IEEE, 2006)

Product-Term-Based Synthesizable Embedded Programmable Logic Cores. - Andy Yan; Steven J. E. Wilton (IEEE Trans. Very Large Scale Integr. Syst., 2006)

GlitchLess: an active glitch minimization technique for FPGAs. - Julien Lamoureux; Guy G. Lemieux; Steven J. E. Wilton (FPGA, 2007)

A synthesizable datapath-oriented embedded FPGA fabric. - Steven J. E. Wilton; Chun Hok Ho; Philip Heng Wai Leong; Wayne Luk; Bradley R. Quinton (FPGA, 2007)

Domain-Specific Hybrid FPGA: Architecture and Floating Point Applications. - Chun Hok Ho; Chi Wai Yu; Philip Heng Wai Leong; Wayne Luk; Steven J. E. Wilton (FPL, 2007)

Clock-Aware Placement for FPGAs. - Julien Lamoureux; Steven J. E. Wilton (FPL, 2007)

Embedded Programmable Logic Core Enhancements for System Bus Interfaces. - Bradley R. Quinton; Steven J. E. Wilton (FPL, 2007)

Memory Footprint Reduction for FPGA Routing Algorithms. - Scott Y. L. Chin; Steven J. E. Wilton (FPT, 2007)

Session 14 - Advanced SoCs - techniques and applications. - Steven J. E. Wilton; Arif Rahman (CICC, 2008)

BackSpace: Formal Analysis for Post-Silicon Debug. - Flavio M. de Paula; Marcel Gort; Alan J. Hu; Steven J. E. Wilton; Jin Yang 006 (FMCAD, 2008)

Rapid estimation of power consumption for hybrid FPGAs. - Chun Hok Ho; Philip Heng Wai Leong; Wayne Luk; Steven J. E. Wilton (FPL, 2008)

An analytical model describing the relationships between logic architecture and FPGA density. - Andrew Lam; Steven J. E. Wilton; Philip Heng Wai Leong; Wayne Luk (FPL, 2008)

A system-level stochastic circuit generator for FPGA architecture evaluation. - Cindy Mark; Ava Shui; Steven J. E. Wilton (FPT, 2008)

Optimizing coarse-grained units in floating point hybrid FPGA. - Chi Wai Yu; Alastair M. Smith; Wayne Luk; Philip Heng Wai Leong; Steven J. E. Wilton (FPT, 2008)

BackSpace: Moving Towards Reality. - Flavio M. de Paula; Marcel Gort; Alan J. Hu; Steven J. E. Wilton (MTV, 2008)

On the Power Dissipation of Embedded Memory Blocks Used to Implement Logic in Field-Programmable Gate Arrays. - Scott Y. L. Chin; Clarence S. P. Lee; Steven J. E. Wilton (Int. J. Reconfigurable Comput., 2008)

The Coarse-Grained/Fine-Grained Logic Interface in FPGAs with Embedded Floating-Point Arithmetic Units. - Chi Wai Yu; Julien Lamoureux; Steven J. E. Wilton; Philip Heng Wai Leong; Wayne Luk (Int. J. Reconfigurable Comput., 2008)

On the trade-off between power and flexibility of FPGA clock networks. - Julien Lamoureux; Steven J. E. Wilton (ACM Trans. Reconfigurable Technol. Syst., 2008)

A Synthesizable Datapath-Oriented Embedded FPGA Fabric for Silicon Debug Applications. - Steven J. E. Wilton; Chun Hok Ho; Bradley R. Quinton; Philip Heng Wai Leong; Wayne Luk (ACM Trans. Reconfigurable Technol. Syst., 2008)

GlitchLess: Dynamic Power Minimization in FPGAs Through Edge Alignment and Glitch Filtering. - Julien Lamoureux; Guy G. Lemieux; Steven J. E. Wilton (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Practical Asynchronous Interconnect Network Design. - Bradley R. Quinton; Mark R. Greenstreet; Steven J. E. Wilton (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Field-Programmable Gate Array Architectures. - Steven J. E. Wilton; Nathalie Chan King Choy; Scott Y. L. Chin; Kara K. W. Poon (Handbook of Algorithms for Physical Design Automation, 2008)

Charge-borrowing decap: A novel circuit for removal of local supply noise violations. - Xiongfei Meng; Resve A. Saleh; Steven J. E. Wilton (CICC, 2009)

Wirelength modeling for homogeneous and heterogeneous FPGA architectural development. - Alastair M. Smith; Steven J. E. Wilton; Joydip Das (FPGA, 2009)

An analytical model relating FPGA architecture and place and route runtime. - Scott Y. L. Chin; Steven J. E. Wilton (FPL, 2009)

Improving the memory footprint and runtime scalability of FPGA CAD algorithms. - Scott Y. L. Chin; Steven J. E. Wilton (FPL, 2009)

Modeling post-techmapping and post-clustering FPGA circuit depth. - Joydip Das; Steven J. E. Wilton; Philip Heng Wai Leong; Wayne Luk (FPL, 2009)

A detailed delay path model for FPGAs. - Eddie Hung; Steven J. E. Wilton; Haile Yu; Thomas C. P. Chau; Philip Heng Wai Leong (FPT, 2009)

Concurrently optimizing FPGA architecture parameters and transistor sizing: Implications for FPGA design. - Alastair M. Smith; George A. Constantinides; Steven J. E. Wilton; Peter Y. K. Cheung (FPT, 2009)

Simultaneous PVT-tolerant voltage-island formation and core placement for thousand-core platforms. - Sohaib Majzoub; Resve A. Saleh; Steven J. E. Wilton; Rabab Ward (SoC, 2009)

Removal-Cost Method: An efficient voltage selection algorithm for multi-core platforms under PVT. - Sohaib Majzoub; Resve A. Saleh; Steven J. E. Wilton; Rabab Kreidieh Ward (SoCC, 2009)

Static and Dynamic Memory Footprint Reduction for FPGA Routing Algorithms. - Scott Y. L. Chin; Steven J. E. Wilton (ACM Trans. Reconfigurable Technol. Syst., 2009)

Floating-Point FPGA: Architecture and Modeling. - Chun Hok Ho; Chi Wai Yu; Philip Heng Wai Leong; Wayne Luk; Steven J. E. Wilton (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Programmable Logic Core Enhancements for High-Speed On-Chip Interfaces. - Bradley R. Quinton; Steven J. E. Wilton (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Towards Analytical Methods for FPGA Architecture Investigation. - Steven J. E. Wilton (ARC, 2010)

The impact of interconnect architecture on via-programmed structured ASICs (VPSAs). - Usman Ahmed; Guy G. Lemieux; Steven J. E. Wilton (FPGA, 2010)

An FPGA architecture supporting dynamically controlled power gating. - Assem A. M. Bsoul; Steven J. E. Wilton (FPT, 2010)

Accelerating trace computation in post-silicon debug. - Johnny J. W. Kuan; Steven J. E. Wilton; Tor M. Aamodt (ISQED, 2010)

Energy Optimization for Many-Core Platforms: Communication and PVT Aware Voltage-Island Formation and Voltage Selection Algorithm. - Sohaib Majzoub; Resve A. Saleh; Steven J. E. Wilton; Rabab K. Ward (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Towards scalable FPGA CAD through architecture. - Scott Y. L. Chin; Steven J. E. Wilton (FPGA, 2011)

An analytical model relating FPGA architecture parameters to routability. - Joydip Das; Steven J. E. Wilton (FPGA, 2011)

Speculative Debug Insertion for FPGAs. - Eddie Hung; Steven J. E. Wilton (FPL, 2011)

Accelerated FPGA architecture design: Capabilities and limitations of analytical models. - Joydip Das; Steven J. E. Wilton (FPT, 2011)

Sequence pair based voltage island floorplanning. - Dipanjan Sengupta; Andreas G. Veneris; Steven J. E. Wilton; André Ivanov; Res Saleh (IGCC, 2011)

On evaluating signal selection algorithms for post-silicon debug. - Eddie Hung; Steven J. E. Wilton (ISQED, 2011)

Deterministic Timing-Driven Parallel Placement by Simulated Annealing Using Half-Box Window Decomposition. - Jeffrey B. Goeders; Guy G. F. Lemieux; Steven J. E. Wilton (ReConFig, 2011)

Performance and Cost Tradeoffs in Metal-Programmable Structured ASICs (MPSAs). - Usman Ahmed; Guy G. Lemieux; Steven J. E. Wilton (IEEE Trans. Very Large Scale Integr. Syst., 2011)

An Analytical Model Relating FPGA Architecture to Logic Density and Depth. - Joydip Das; Andrew Lam; Steven J. E. Wilton; Philip Heng Wai Leong; Wayne Luk (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Advances in 3D design and optimization. - Steven J. E. Wilton; Visvesh S. Sathe 001 (CICC, 2012)

A configurable architecture to limit wakeup current in dynamically-controlled power-gated FPGAs. - Assem A. M. Bsoul; Steven J. E. Wilton (FPGA, 2012)

Limitations of incremental signal-tracing for FPGA debug. - Eddie Hung; Steven J. E. Wilton (FPL, 2012)

An FPGA with power-gated switch blocks. - Assem A. M. Bsoul; Steven J. E. Wilton (FPT, 2012)

VersaPower: Power estimation for diverse FPGA architectures. - Jeffrey B. Goeders; Steven J. E. Wilton (FPT, 2012)

Rapid RTL-based signal ranking for FPGA prototyping. - Steven J. E. Wilton; Bradley R. Quinton; Eddie Hung (FPT, 2012)

Emulation in post-silicon validation: It's not just for functionality anymore. - Kyle Balston; Alan J. Hu; Steven J. E. Wilton; Amir Nahir (HLDVT, 2012)

Multi-objective voltage island floorplanning using sequence pair representation. - Dipanjan Sengupta; Andreas G. Veneris; Steven J. E. Wilton; André Ivanov (Sustain. Comput. Informatics Syst., 2012)

Hierarchical Benchmark Circuit Generation for FPGA Architecture Evaluation. - Cindy Mark; Scott Y. L. Chin; Lesley Shannon; Steven J. E. Wilton (ACM Trans. Embed. Comput. Syst., 2012)

Formal-Analysis-Based Trace Computation for Post-Silicon Debug. - Marcel Gort; Flavio M. de Paula; Johnny J. W. Kuan; Tor M. Aamodt; Alan J. Hu; Steven J. E. Wilton; Jin Yang 006 (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Optimizing Floating Point Units in Hybrid FPGAs. - Chi Wai Yu; Alastair M. Smith; Wayne Luk; Philip Heng Wai Leong; Steven J. E. Wilton (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Escaping the Academic Sandbox: Realizing VPR Circuits on Xilinx Devices. - Eddie Hung; Fatemeh Eslami; Steven J. E. Wilton (FCCM, 2013)

Towards simulator-like observability for FPGAs: a virtual overlay network for trace-buffers. - Eddie Hung; Steven J. E. Wilton (FPGA, 2013)

Maximum flow algorithms for maximum observability during FPGA debug. - Eddie Hung; Al-Shahna Jamal; Steven J. E. Wilton (FPT, 2013)

Linking the Verification and Validation of Complex Integrated Circuits Through Shared Coverage Metrics. - Eddie Hung; Bradley R. Quinton; Steven J. E. Wilton (IEEE Des. Test, 2013)

Post-Silicon Code Coverage for Multiprocessor System-on-Chip Designs. - Kyle Balston; Mehdi Karimibiuki; Alan J. Hu; André Ivanov; Steven J. E. Wilton (IEEE Trans. Computers, 2013)

Towards development of an analytical model relating FPGA architecture parameters to routability. - Joydip Das; Steven J. E. Wilton (ACM Trans. Reconfigurable Technol. Syst., 2013)

Scalable Signal Selection for Post-Silicon Debug. - Eddie Hung; Steven J. E. Wilton (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Faster FPGA Debug: Efficiently Coupling Trace Instruments with User Circuitry. - Eddie Hung; Jeffrey B. Goeders; Steven J. E. Wilton (ARC, 2014)

High-level synthesis-based design methodology for Dynamic Power-Gated FPGAs. - Rehan Ahmed; Assem A. M. Bsoul; Steven J. E. Wilton; Peter Hallschmid; Richard Klukas (FPL, 2014)

Incremental distributed trigger insertion for efficient FPGA debug. - Fatemeh Eslami; Steven J. E. Wilton (FPL, 2014)

Effective FPGA debug for high-level synthesis generated circuits. - Jeffrey B. Goeders; Steven J. E. Wilton (FPL, 2014)

A Configurable Architecture to Limit Inrush Current in Power-Gated Reconfigurable Devices. - Assem A. M. Bsoul; Steven J. E. Wilton (J. Low Power Electron., 2014)

Power Aware Architecture Exploration for Field Programmable Gate Arrays. - Jeffrey B. Goeders; Steven J. E. Wilton (J. Low Power Electron., 2014)

Accelerating FPGA debug: Increasing visibility using a runtime reconfigurable observation and triggering network. - Eddie Hung; Steven J. E. Wilton (ACM Trans. Design Autom. Electr. Syst., 2014)

Incremental Trace-Buffer Insertion for FPGA Debug. - Eddie Hung; Steven J. E. Wilton (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Hierarchical Dynamic Power-Gating in FPGAs. - Rehan Ahmed; Steven J. E. Wilton; Peter Hallschmid; Richard Klukas (ARC, 2015)

Using Dynamic Signal-Tracing to Debug Compiler-Optimized HLS Circuits on FPGAs. - Jeffrey B. Goeders; Steven J. E. Wilton (FCCM, 2015)

An adaptive virtual overlay for fast trigger insertion for FPGA debug. - Fatemeh Eslami; Steven J. E. Wilton (FPT, 2015)

Using Round-Robin Tracepoints to debug multithreaded HLS circuits on FPGAs. - Jeffrey Goeders; Steven J. E. Wilton (FPT, 2015)

RAW Introduction and Committees. - Jürgen Becker 001; Ken Eguro; Diana Göhringer; Wayne Luk; Marco D. Santambrogio; Ramachandran Vaidyanathan; Steven J. E. Wilton (IPDPS Workshops, 2015)

Allowing Software Developers to Debug HLS Hardware. - Jeffrey B. Goeders; Steven J. E. Wilton (CoRR, 2015)

Systems-on-Chip on FPGAs. - Jeffrey B. Goeders; Graham M. Holland; Lesley Shannon; Steven J. E. Wilton (FPGAs for Software Programmers, 2016)

Quantifying observability for in-system debug of high-level synthesis circuits. - Jeffrey Goeders; Steven J. E. Wilton (FPL, 2016)

Enhanced source-level instrumentation for FPGA in-system debug of High-Level Synthesis designs. - Jose P. Pinilla; Steven J. E. Wilton (FPT, 2016)

RAW Introduction and Committees. - Marco D. Santambrogio; Ramachandran Vaidyanathan; Diana Goehringer; Steven J. E. Wilton (IPDPS Workshops, 2016)

Enabling Effective FPGA Debug using Overlays: Opportunities and Challenges. - Fatemeh Eslami; Eddie Hung; Steven J. E. Wilton (CoRR, 2016)

An Improved Overlay and Mapping Algorithm Supporting Rapid Triggering for FPGA Debug. - Fatemeh Eslami; Steven J. E. Wilton (SIGARCH Comput. Archit. News, 2016)

An FPGA Architecture and CAD Flow Supporting Dynamically Controlled Power Gating. - Assem A. M. Bsoul; Steven J. E. Wilton; Kuen Hung Tsoi; Wayne Luk (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Accelerating in-system FPGA debug of high-level synthesis circuits using incremental compilation techniques. - Pavan Kumar Bussa; Jeffrey Goeders; Steven J. E. Wilton (FPL, 2017)

Rapid circuit-specific inlining tuning for FPGA high-level synthesis. - Daniel H. Noronha; Jose P. Pinilla; Steven J. E. Wilton (ReConFig, 2017)

Signal-Tracing Techniques for In-System FPGA Debugging of High-Level Synthesis Circuits. - Jeffrey Goeders; Steven J. E. Wilton (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Extending post-silicon coverage measurement using time-multiplexed FPGA overlays. - Fatemeh Eslami; Eddie Hung; Steven J. E. Wilton (ETS, 2018)

Architecture Exploration for HLS-Oriented FPGA Debug Overlays. - Al-Shahna Jamal; Jeffrey Goeders; Steven J. E. Wilton (FPGA, 2018)

An FPGA Overlay Architecture Supporting Rapid Implementation of Functional Changes during On-Chip Debug. - Al-Shahna Jamal; Jeffrey Goeders; Steven J. E. Wilton (FPL, 2018)

Simultaneous Inference and Training Using On-FPGA Weight Perturbation Techniques. - Siddhartha 003; Steven J. E. Wilton; David Boland; Barry Flower; Perry Blackmore; Philip H. W. Leong (FPT, 2018)

LeFlow: Automatic Compilation of TensorFlow Machine Learning Applications to FPGAs. - Daniel Holanda Noronha; Kahlan Gibson; Bahar Salehpour; Steven J. E. Wilton (FPT, 2018)

Kibo: An Open-Source Fixed-Point Tool-kit for Training and Inference in FPGA-Based Deep Learning Networks. - Daniel Holanda Noronha; Philip Heng Wai Leong; Steven J. E. Wilton (IPDPS Workshops, 2018)

LeFlow: Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks. - Daniel H. Noronha; Bahar Salehpour; Steven J. E. Wilton (CoRR, 2018)

Rapid Triggering Capability Using an Adaptive Overlay during FPGA Debug. - Fatemeh Eslami; Steven J. E. Wilton (ACM Trans. Design Autom. Electr. Syst., 2018)

Introduction to the Special Section on Deep Learning in FPGAs. - Deming Chen; Andrew Putnam; Steven J. E. Wilton (ACM Trans. Reconfigurable Technol. Syst., 2018)

On-chip FPGA Debug Instrumentation for Machine Learning Applications. - Daniel Holanda Noronha; Ruizhe Zhao; Jeffrey Goeders; Wayne Luk; Steven J. E. Wilton (FPGA, 2019)

Towards In-Circuit Tuning of Deep Learning Designs. - Zhiqiang Que; Daniel Holanda Noronha; Ruizhe Zhao; Steven J. E. Wilton; Wayne Luk (ICCAD, 2019)

An Overlay for Rapid FPGA Debug of Machine Learning Applications. - Daniel Holanda Noronha; Ruizhe Zhao; Zhiqiang Que; Jeffrey Goeders; Wayne Luk; Steven J. E. Wilton (FPT, 2019)

Layout-Aware Embedding for Quantum Annealing Processors. - Jose P. Pinilla; Steven J. E. Wilton (ISC, 2019)

Syncopation: Adaptive Clock Management for High-Level Synthesis Generated Circuits on FPGAs. - Kahlan Gibson; Esther Roorda; Daniel Holanda Noronha; Steven J. E. Wilton (FPL, 2020)

Towards Overlay-based Rapid In-Circuit Tuning of Deep Learning Designs. - Zhiqiang Que; Daniel Holanda Noronha; Ruizhe Zhao; Xinyu Niu; Steven J. E. Wilton; Wayne Luk (FPT, 2020)

Fast Turnaround HLS Debugging Using Dependency Analysis and Debug Overlays. - Al-Shahna Jamal; Eli Cahill; Jeffrey Goeders; Steven J. E. Wilton (ACM Trans. Reconfigurable Technol. Syst., 2020)

Flexible Instrumentation for Live On-Chip Debug of Machine Learning Training on FPGAs. - Daniel Holanda Noronha; Zhiqiang Que; Wayne Luk; Steven J. E. Wilton (FCCM, 2021)

MAFIA: Machine Learning Acceleration on FPGAs for IoT Applications. - Nikhil Pratap Ghanathe; Vivek Seshadri; Rahul Sharma 001; Steve Wilton; Aayan Kumar (FPL, 2021)

In-circuit tuning of deep learning designs. - Zhiqiang Que; Daniel Holanda Noronha; Ruizhe Zhao; Xinyu Niu; Steven J. E. Wilton; Wayne Luk (J. Syst. Archit., 2021)

Boosting Domain-Specific Debug Through Inter-frame Compression. - Zakary Nafziger; Martin Chua; Daniel Holanda Noronha; Steven J. E. Wilton (FPT, 2022)

Positive-Phase Temperature Scaling for Quantum-Assisted Boltzmann Machine Training. - Jose P. Pinilla; Steven J. E. Wilton (SC, 2022)

Adaptive Clock Management of HLS-generated Circuits on FPGAs. - Kahlan Gibson; Esther Roorda; Daniel Holanda Noronha; Steven J. E. Wilton (ACM Trans. Reconfigurable Technol. Syst., 2022)

Rethinking Embedded Blocks for Machine Learning Applications. - Seyedramin Rasoulinezhad; Esther Roorda; Steve Wilton; Philip H. W. Leong; David Boland (ACM Trans. Reconfigurable Technol. Syst., 2022)

FPGA Architecture Exploration for DNN Acceleration. - Esther Roorda; Seyedramin Rasoulinezhad; Philip H. W. Leong; Steven J. E. Wilton (ACM Trans. Reconfigurable Technol. Syst., 2022)

T-RecX: Tiny-Resource Efficient Convolutional neural networks with early-eXit. - Nikhil Pratap Ghanathe; Steve Wilton (CF, 2023)

A Machine Learning Approach for Predicting the Difficulty of FPGA Routing Problems. - Andrew David Gunter; Steven J. E. Wilton (FCCM, 2023)

Reformulating the FPGA Routability Prediction Problem with Machine Learning. - Andrew David Gunter; Steve Wilton (FCCM, 2023)

Designing a configurable IEEE-compliant FPU that supports variable precision for soft processors. - Chris Keilbart; Yuhui Gao; Martin Chua; Eric Matthews; Steven J. E. Wilton; Lesley Shannon (FCCM, 2023)

Towards a Machine Learning Approach to Predicting the Difficulty of FPGA Routing Problems. - Andrew David Gunter; Steven J. E. Wilton (FPGA, 2023)

Online Training from Streaming Data with Concept Drift on FPGAs. - Esther Roorda; Steven J. E. Wilton (ISQED, 2023)

A Semi Black-Box Adversarial Bit- Flip Attack with Limited DNN Model Information. - Behnam Ghavami; Mani Sadati; Mohammad Shahidzadeh; Lesley Shannon; Steve Wilton (ICCD, 2024)

ZOBNN: Zero-Overhead Dependable Design of Binary Neural Networks with Deliberately Quantized Parameters. - Behnam Ghavami; Mohammad Shahidzadeh; Lesley Shannon; Steve Wilton (IOLTS, 2024)

DNN Memory Footprint Reduction via Post-Training Intra-Layer Multi-Precision Quantization. - Behnam Ghavami; Amin Kamjoo; Lesley Shannon; Steve Wilton (ISQED, 2024)

Boosting Multiple Multipliers Packing on FPGA DSP Blocks via Truncation and Compensation-based Approximation. - Behnam Ghavami; Mahdi Sajadi; Lesley Shannon; Steve Wilton (ISVLSI, 2024)

Enabling Risk Management of Machine Learning Predictions for FPGA Routability. - Andrew David Gunter; Maya Thomas; Nikhil Pratap Ghanathe; Steven J. E. Wilton (MLCAD, 2024)

Machine Learning VLSI CAD Experiments Should Consider Atomic Data Groups. - Andrew David Gunter; Steven J. E. Wilton (MLCAD, 2024)

Structural Modifications in Quantum-Assisted Training for General Boltzmann Machines. - Jose P. Pinilla; Steven J. E. Wilton (QCE, 2024)

Quantum-Assisted Machine Learning Framework: Training and Evaluation of Boltzmann Machines Using Quantum Annealers. - Jose P. Pinilla; Steven J. E. Wilton (QCE, 2024)

QUTE: Quantifying Uncertainty in TinyML models with Early-exit-assisted ensembles. - Nikhil Pratap Ghanathe; Steve Wilton (CoRR, 2024)

DEBUG-HD: Debugging TinyML models on-device using Hyper-Dimensional computing. - Nikhil Pratap Ghanathe; Steven J. E. Wilton (CoRR, 2024)

Automatic High-quality Verilog Assertion Generation through Subtask-Focused Fine-Tuned LLMs and Iterative Prompting. - Mohammad Shahidzadeh; Behnam Ghavami; Steve Wilton; Lesley Shannon (CoRR, 2024)

Designing an IEEE-Compliant FPU that Supports Configurable Precision for Soft Processors. - Chris Keilbart; Yuhui Gao; Martin Chua; Eric Matthews; Steven J. E. Wilton; Lesley Shannon (ACM Trans. Reconfigurable Technol. Syst., 2024)

Chronbench: An Incremental HDL Benchmark Suite. - Zakary Nafziger; Steven J. E. Wilton (FCCM, 2025)

Automated Verilog Assertion Generation Using Fine-Tuned LLMs with Subtask-Specific Iterative Prompting. - Mohammad Shahidzadeh; Behnam Ghavami; Steven J. E. Wilton; Lesley Shannon (ISQED, 2025)