MIPS: A microprocessor architecture. - John L. Hennessy; Norman P. Jouppi; Steven A. Przybylski; Christopher Rowen; Thomas R. Gross; Forest Baskett; John Gill (MICRO, 1982)

A CMOS RISC Processor with Integrated System Functions. - John P. Moussouris; Lester M. Crudele; Danny Freitas; Craig Hansen; Ed Hudson; Roger March; Steven A. Przybylski; Tim Riordan; Chris Rowen; D. Van't Hof (COMPCON, 1986)

Performance Tradeoffs in Cache Design. - Steven A. Przybylski; Mark Horowitz; John L. Hennessy (ISCA, 1988)

Measurement and Evaluation of the MIPS Architecture and Processor. - Thomas R. Gross; John L. Hennessy; Steven A. Przybylski; Christopher Rowen (ACM Trans. Comput. Syst., 1988)

Characteristics of Performance-Optimal Multi-Level Cache Hierarchies. - Steven A. Przybylski; Mark Horowitz; John L. Hennessy (ISCA, 1989)

The Performance Impact of Block Sizes and Fetch Strategies. - Steven A. Przybylski (ISCA, 1990)

An analytical access time model for on-chip cache memories. - Tomohisa Wada; Suresh Rajan; Steven A. Przybylski (IEEE J. Solid State Circuits, 1992)

Common Bonds: MIPS, HPS, Two-Level Branch Prediction, and Compressed Code RISC Processor. - Onur Mutlu; Rich Belgard; Thomas R. Gross; Norman P. Jouppi; John L. Hennessy; Steven A. Przybylski; Chris Rowen; Yale N. Patt; Wen-mei W. Hwu; Stephen W. Melvin; Michael Shebanow; Tse-Yu Yeh; et al. (IEEE Micro, 2016)