A 5.6-ns random cycle 144-Mb DRAM with 1.4 Gb/s/pin and DDR3-SRAM interface. - Harold Pilo; Darren Anand; John Barth 001; Steve Burns 001; Phil Corson; Jim Covino; Steve Lamphier (IEEE J. Solid State Circuits, 2003)

A 500-MHz multi-banked compilable DRAM macro with direct write and programmable pipelining. - John E. Barth Jr.; Darren Anand; Steve Burns 001; Jeffrey H. Dreibelbis; John A. Fifield; Kevin W. Gorman; Michael R. Nelms; Erik Nelson; Adrian Paparelli; Gary Pomichter; Dale E. Pontius; Stephen Sliva (IEEE J. Solid State Circuits, 2005)

Isolated Preset Architecture for a 32nm SOI embedded DRAM macro. - John Barth 001; Don Plass; Adis Vehabovic; Rajiv V. Joshi; Rouwaida Kanj; Steven Burns 001; Todd Weaver (VLSIC, 2012)

17.4 A 14nm 1.1Mb embedded DRAM macro with 1ns access. - Gregory Fredeman; Donald W. Plass; Abraham Mathews; Kenneth Reyer; Thomas J. Knips; Thomas Miller; Elizabeth L. Gerhard; Dinesh Kannambadi; Chris Paone; Dongho Lee; Daniel Rainey 002; Michael A. Sperling; et al. (ISSCC, 2015)

A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access. - Gregory Fredeman; Donald W. Plass; Abraham Mathews; Janakiraman Viraraghavan; Kenneth Reyer; Thomas J. Knips; Thomas Miller; Elizabeth L. Gerhard; Dinesh Kannambadi; Chris Paone; Dongho Lee; Daniel Rainey 002; et al. (IEEE J. Solid State Circuits, 2016)

12.4 1.4Gsearch/s 2Mb/mm2 TCAM using two-phase-precharge ML sensing and power-grid preconditioning to reduce Ldi/dt power-supply noise by 50%. - Igor Arsovski; Michael Fragano; Robert M. Houle; Akhilesh Patil; Van Butler; Raymond Kim; Ramon Rodriguez; Tom Maffitt; Joseph J. Oler; John Goss; Christopher Parkinson; Michael A. Ziegerhofer; et al. (ISSCC, 2017)