FCCMS and the Memory Wall. - Steven Derrien; Sanjay V. Rajopadhye (FCCM, 2000)

Approximating a Single Viewpoint in Panoramic Imaging Devices. - Steven Derrien; Kurt Konolige (ICRA, 2000)

Optimal Partitioning for FPGA Based Regular Array Implementations. - Steven Derrien; Sanjay V. Rajopadhye; Susmita Sur-Kolay (PARELEC, 2000)

Interfacing compiled FPGA programs: the MMAlpha approach. - Steven Derrien; Tanguy Risset (PDPTA, 2000)

Combining Instruction and Loop Level Parallelism for FPGAs. - Steven Derrien; Sanjay V. Rajopadhye; Susmita Sur-Kolay (FCCM, 2001)

Loop Tiling for Reconfigurable Accelerators. - Steven Derrien; Sanjay V. Rajopadhye (FPL, 2001)

Combined instruction and loop parallelism in array synthesis for FPGAs. - Steven Derrien; Sanjay V. Rajopadhye; Susmita Sur-Kolay (ISSS, 2001)

Energy/Power Estimation of Regular Processor Arrays. - Sanjay V. Rajopadhye; Steven Derrien (ISSS, 2002)

A Reconfigurable Parallel Disk System for Filtering Genomic Banks. - Dominique Lavenier; Stéphane Guyetant; Steven Derrien; Stéphane Rubini (Engineering of Reconfigurable Systems and Algorithms, 2003)

Hardware/Software Interface for Multi-Dimensional Processor Arrays. - Alain Darte; Steven Derrien; Tanguy Risset (ASAP, 2005)

Cluster of re-configurable nodes for scanning large genomic banks. - Stéphane Guyetant; Mathieu Giraud; Ludovic L'Hours; Steven Derrien; Stéphane Rubini; Dominique Lavenier; Frédéric Raimbault (Parallel Comput., 2005)

Acceleration of a content-based image-retrieval application on the RDISK cluster. - Auguste Noumsi; Steven Derrien; Patrice Quinton (IPDPS, 2006)

Combining Flash Memory and FPGAs to Efficiently Implement a Massively Parallel Algorithm for Content-Based Image Retrieval. - Rayan Chikhi; Steven Derrien; Auguste Noumsi; Patrice Quinton (ARC, 2007)

Parallelizing HMMER for Hardware Acceleration on FPGAs. - Steven Derrien; Patrice Quinton (ASAP, 2007)

Deriving efficient control in Process Networks with Compaan/Laura. - Steven Derrien; Alexandru Turjan; Claudiu Zissulescu; Bart Kienhuis; Ed F. Deprettere (Int. J. Embed. Syst., 2008)

Ultra Low-power FSM for Control Oriented Applications. - Muhammad Adeel Pasha; Steven Derrien; Olivier Sentieys (ISCAS, 2009)

A complete design-flow for the generation of ultra low-power WSN node architectures based on micro-tasking. - Muhammad Adeel Pasha; Steven Derrien; Olivier Sentieys (DAC, 2010)

System Level Synthesis for Ultra Low-Power Wireless Sensor Nodes. - Muhammad Adeel Pasha; Steven Derrien; Olivier Sentieys (DSD, 2010)

Accelerating HMMER on FPGA using parallel prefixes and reductions. - Naeem Abbas; Steven Derrien; Sanjay V. Rajopadhye; Patrice Quinton (FPT, 2010)

Hardware Acceleration of HMMER on FPGAs. - Steven Derrien; Patrice Quinton (J. Signal Process. Syst., 2010)

Contributions à la conception d'architectures matérielles dédiées. - Steven Derrien (2011)

HLS Tools for FPGA: Faster Development with Better Performance. - Alexandre Cornu; Steven Derrien; Dominique Lavenier (ARC, 2011)

Efficient nested loop pipelining in high level synthesis using polyhedral bubble insertion. - Antoine Morvan; Steven Derrien; Patrice Quinton (FPT, 2011)

ompVerify: Polyhedral Analysis for the OpenMP Programmer. - V. Basupalli; Tomofumi Yuki; Sanjay V. Rajopadhye; Antoine Morvan; Steven Derrien; Patrice Quinton; David Wonnacott (IWOMP, 2011)

Model-Driven Engineering and Optimizing Compilers: A Bridge Too Far? - Antoine Floch; Tomofumi Yuki; Clément Guy; Steven Derrien; Benoît Combemale; Sanjay V. Rajopadhye; Robert B. France (MoDELS, 2011)

Wakeup Time and Wakeup Energy Estimation in Power-Gated Logic Clusters. - Vivek D. Tovinakere; Olivier Sentieys; Steven Derrien (VLSI Design, 2011)

A Polynomial Based Approach to Wakeup Time and Energy Estimation in Power-Gated Logic Clusters. - Vivek D. Tovinakere; Olivier Sentieys; Steven Derrien (J. Low Power Electron., 2011)

A Compilation- and Simulation-Oriented Architecture Description Language for Multicore Systems. - Timo Stripf; Oliver Oey; Thomas Bruckschlögl; Ralf König 001; George Goulas; Panayiotis Alefragis; Nikolaos S. Voros; Jordy Potman; Kim Sunesen; Steven Derrien; Olivier Sentieys; Jürgen Becker 001 (CSE, 2012)

A semiempirical model for wakeup time estimation in power-gated logic clusters. - Vivek D. Tovinakere; Olivier Sentieys; Steven Derrien (DAC, 2012)

From Scilab to High Performance Embedded Multicore Systems: The ALMA Approach. - Jürgen Becker 001; Timo Stripf; Oliver Oey; Michael Hübner 001; Steven Derrien; Daniel Ménard; Olivier Sentieys; Gerard K. Rauwerda; Kim Sunesen; Nikolaos Kavvadias; Kostas Masselos; George Goulas; et al. (DSD, 2012)

On Model Subtyping. - Clément Guy; Benoît Combemale; Steven Derrien; Jim Steel; Jean-Marc Jézéquel (ECMFA, 2012)

A flexible approach for compiling scilab to reconfigurable multi-core embedded systems. - Timo Stripf; Oliver Oey; Thomas Bruckschlögl; Ralf König 001; Michael Hübner 001; Jürgen Becker 001; Gerard K. Rauwerda; Kim Sunesen; Nikolaos Kavvadias; Grigoris Dimitroulakos; Kostas Masselos; Dimitrios Kritharidis; et al. (ReCoSoC, 2012)

From Scilab to multicore embedded systems: Algorithms and methodologies. - George Goulas; Panayiotis Alefragis; Nikolaos S. Voros; Christos Valouxis; Christos Gogos; Nikolaos Kavvadias; Grigoris Dimitroulakos; Kostas Masselos; Diana Göhringer; Steven Derrien; Daniel Ménard; Olivier Sentieys; et al. (ICSAMOS, 2012)

Efficient hardware implementation of data-flow parallel embedded systems. - Patrice Quinton; Anne-Marie Chana; Steven Derrien (ICSAMOS, 2012)

Bridging the chasm between MDE and the world of compilation. - Jean-Marc Jézéquel; Benoît Combemale; Steven Derrien; Clément Guy; Sanjay V. Rajopadhye (Softw. Syst. Model., 2012)

System-Level Synthesis for Wireless Sensor Node Controllers: A Complete Design Flow. - Muhammad Adeel Pasha; Steven Derrien; Olivier Sentieys (ACM Trans. Design Autom. Electr. Syst., 2012)

Runtime dependency analysis for loop pipelining in high-level synthesis. - Mythri Alle; Antoine Morvan; Steven Derrien (DAC, 2013)

Component-Level Datapath Merging in System-Level Design of Wireless Sensor Node Controllers for FPGA-Based Implementations. - Muhammad Adeel Pasha; Steven Derrien; Olivier Sentieys (DSD, 2013)

Using Model Types to Support Contract-Aware Model Substitutability. - Wuliang Sun; Benoît Combemale; Steven Derrien; Robert B. France (ECMFA, 2013)

Derivation of efficient FSM from loop nests. - Tomofumi Yuki; Antoine Morvan; Steven Derrien (FPT, 2013)

GeCoS: A framework for prototyping custom hardware design flows. - Antoine Floch; Tomofumi Yuki; Ali El Moussawi; Antoine Morvan; Kevin J. M. Martin; Maxime Naullet; Mythri Alle; Ludovic L'Hours; Nicolas Simon; Steven Derrien; François Charot; Christophe Wolinski; et al. (SCAM, 2013)

Compiling Scilab to high performance embedded multicore systems. - Timo Stripf; Oliver Oey; Thomas Bruckschlögl; Jürgen Becker 001; Gerard K. Rauwerda; Kim Sunesen; George Goulas; Panayiotis Alefragis; Nikolaos S. Voros; Steven Derrien; Olivier Sentieys; Nikolaos Kavvadias; et al. (Microprocess. Microsystems, 2013)

Polyhedral Bubble Insertion: A Method to Improve Nested Loop Pipelining for High-Level Synthesis. - Antoine Morvan; Steven Derrien; Patrice Quinton (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Low Power Reconfigurable Controllers for Wireless Sensor Network Nodes. - Vivek D. Tovinakere; Olivier Sentieys; Steven Derrien; Christophe Huriaux (FCCM, 2014)

Toward scalable source level accuracy analysis for floating-point to fixed-point conversion. - Gaël Deest; Tomofumi Yuki; Olivier Sentieys; Steven Derrien (ICCAD, 2014)

Component reuse methodology for multi-clock Data-Flow parallel embedded Systems. - Anne-Marie Chana; Patrice Quinton; Steven Derrien (ARIMA J., 2014)

Combining execution pipelines to improve parallel implementation of HMMER on FPGA. - Naeem Abbas; Steven Derrien; Sanjay V. Rajopadhye; Patrice Quinton; Alexandre Cornu; Dominique Lavenier (Microprocess. Microsystems, 2015)

Demo: SLP-aware word length optimization. - Ali Hassan El Moussawi; Steven Derrien (DASIP, 2016)

System level synthesis for virtual memory enabled hardware threads. - Nicolas Estibals; Gaël Deest; Ali Hassan El Moussawi; Steven Derrien (DATE, 2016)

Communication-Based Power Modelling for Heterogeneous Multiprocessor Architectures. - Baptiste Roux; Matthieu Gautier; Olivier Sentieys; Steven Derrien (MCSoC, 2016)

WCET-aware parallelization of model-based applications for multi-cores: The ARGO approach. - Steven Derrien; Isabelle Puaut; Panayiotis Alefragis; Marcus Bednara; Harald Bucher; Clément David; Yann Debray; Umut Durak; Imen Fassi; Christian Ferdinand; Damien Hardy; Angeliki Kritikakou; et al. (DATE, 2017)

Superword level parallelism aware word length optimization. - Ali Hassan El Moussawi; Steven Derrien (DATE, 2017)

Hardware-accelerated dynamic binary translation. - Simon Rokicki; Erven Rohou; Steven Derrien (DATE, 2017)

A High-Level Synthesis Approach Optimizing Accumulations in Floating-Point Programs Using Custom Formats and Operators. - Yohann Uguen; Florent de Dinechin; Steven Derrien (FCCM, 2017)

One size does not fit all: Implementation trade-offs for iterative stencil computations on FPGAs. - Gaël Deest; Tomofumi Yuki; Sanjay V. Rajopadhye; Steven Derrien (FPL, 2017)

Bridging high-level synthesis and application-specific arithmetic: The case study of floating-point summations. - Yohann Uguen; Florent de Dinechin; Steven Derrien (FPL, 2017)

Tightening Contention Delays While Scheduling Parallel Applications on Multi-core Architectures. - Benjamin Rouxel; Steven Derrien; Isabelle Puaut (ACM Trans. Embed. Comput. Syst., 2017)

Foreword to the Special Section on Reconfigurable Computing. - Steven Derrien; Kubilay Atasu; João M. P. Cardoso; Jürgen Becker 001 (J. Signal Process. Syst., 2017)

Using polyhedral techniques to tighten WCET estimates of optimized code: A case study with array contraction. - Thomas Lefeuvre; Imen Fassi; Christoph Cullmann; Gernot Gebhard; Emin-Koray Kasnakli; Isabelle Puaut; Steven Derrien (DATE, 2018)

Supporting runtime reconfigurable VLIWs cores through dynamic binary translation. - Simon Rokicki; Erven Rohou; Steven Derrien (DATE, 2018)

Enabling Overclocking Through Algorithm-Level Error Detection. - Thibaut Marty; Tomofumi Yuki; Steven Derrien (FPT, 2018)

Fine-Grain Iterative Compilation for WCET Estimation. - Isabelle Puaut; Mickaël Dardaillon; Christoph Cullmann; Gernot Gebhard; Steven Derrien (WCET, 2018)

Aggressive Memory Speculation in HW/SW Co-Designed Machines. - Simon Rokicki; Erven Rohou; Steven Derrien (DATE, 2019)

Hiding Communication Delays in Contention-Free Execution for SPM-Based Multi-Core Architectures. - Benjamin Rouxel; Stefanos Skalistis; Steven Derrien; Isabelle Puaut (ECRTS, 2019)

Reconciling Compiler Optimizations and WCET Estimation Using Iterative Compilation. - Mickaël Dardaillon; Stefanos Skalistis; Isabelle Puaut; Steven Derrien (RTSS, 2019)

Hybrid-DBT: Hardware/Software Dynamic Binary Translation Targeting VLIW. - Simon Rokicki; Erven Rohou; Steven Derrien (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Worst-Case Execution-Time-Aware Parallelization of Model-Based Avionics Applications. - Simon Reder; Fabian Kempf; Harald Bucher; Jürgen Becker 001; Panayiotis Alefragis; Nikolaos S. Voros; Stefanos Skalistis; Steven Derrien; Isabelle Puaut; Oliver Oey; Timo Stripf; Christian Ferdinand; et al. (J. Aerosp. Inf. Syst., 2019)

Application-Specific Arithmetic in High-Level Synthesis Tools. - Yohann Uguen; Florent de Dinechin; Victor Lezaud; Steven Derrien (ACM Trans. Archit. Code Optim., 2020)

Toward Speculative Loop Pipelining for High-Level Synthesis. - Steven Derrien; Thibaut Marty; Simon Rokicki; Tomofumi Yuki (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Safe Overclocking for CNN Accelerators Through Algorithm-Level Error Detection. - Thibaut Marty; Tomofumi Yuki; Steven Derrien (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Design Exploration of RISC-V Soft-Cores through Speculative High-Level Synthesis. - Jean-Michel Gorius; Simon Rokicki; Steven Derrien (FPT, 2022)

Maximal Atomic irRedundant Sets: a Usage-based Dataflow Partitioning Algorithm. - Corentin Ferry; Steven Derrien; Sanjay V. Rajopadhye (CoRR, 2022)

SpecHLS: Speculative Accelerator Design Using High-Level Synthesis. - Jean-Michel Gorius; Simon Rokicki; Steven Derrien (IEEE Micro, 2022)

Special Issue on Applied Reconfigurable Computing. - Frank Hannig; Steven Derrien (J. Signal Process. Syst., 2022)

Automatic Algorithm-Based Fault Tolerance (AABFT) of Stencil Computations. - Louis Narmour; Steven Derrien; Sanjay V. Rajopadhye (PACT, 2023)

Rapid Prototyping of Complex Micro-architectures Through High-Level Synthesis. - Sara Sadat Hoseininasab; Caroline Collange; Steven Derrien (ARC, 2023)

An Irredundant Decomposition of Data Flow with Affine Dependences. - Corentin Ferry; Steven Derrien; Sanjay V. Rajopadhye (CoRR, 2023)

Increasing FPGA Accelerators Memory Bandwidth With a Burst-Friendly Memory Layout. - Corentin Ferry; Tomofumi Yuki; Steven Derrien; Sanjay V. Rajopadhye (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

A Unified Memory Dependency Framework for Speculative High-Level Synthesis. - Jean-Michel Gorius; Simon Rokicki; Steven Derrien (CC, 2024)

Efficient Design Space Exploration for Dynamic & Speculative High-Level Synthesis. - Dylan Leothaud; Jean-Michel Gorius; Simon Rokicki; Steven Derrien (FPL, 2024)

An Irredundant and Compressed Data Layout to Optimize Bandwidth Utilization of FPGA Accelerators. - Corentin Ferry; Nicolas Derumigny; Steven Derrien; Sanjay V. Rajopadhye (CoRR, 2024)

Hardware/Software Runtime for GPSA Protection in RISC-V Embedded Cores. - Louis Savary; Simon Rokicki; Steven Derrien (DATE, 2025)