A 20-GHz and 46-GHz, 32x6-bit ROM for DDS Application in InP DHBT Technology. - Sanjeev Manandhar; Steven Eugene Turner; David E. Kotecki (ICECS, 2006)

Direct Digital Synthesizer With Sine-Weighted DAC at 32-GHz Clock Frequency in InP DHBT Technology. - Steven Eugene Turner; David E. Kotecki (IEEE J. Solid State Circuits, 2006)

36-GHz, 16×6-Bit ROM in InP DHBT Technology Suitable for DDS Application. - Sanjeev Manandhar; Steven Eugene Turner; David E. Kotecki (IEEE J. Solid State Circuits, 2007)

Phase Coherent Frequency Hopping in Direct Digital Synthesizers and Phase Locked Loops. - Steven Eugene Turner; Joseph D. Cali (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

A Single-Chip 25.3-28.0 GHz SiGe BiCMOS PLL with -134 dBc/Hz Phase Noise at 10 MHz Offset and -96 dBc Reference Spurs. - Mark D. Hickle; Kevin Grout; Curtis Grens; Gregory M. Flewelling; Steven Eugene Turner (BCICTS, 2021)

Single-Chip 30 GHz SiGe Sub-Sampling PLL with 28.3 fs Jitter. - Dimitre Dimitrov; Mark D. Hickle; Matthew Speir; Joseph M. Krzyzek; Daniel P. Lacroix; Shail Srinivas; Robert Sepanek; Spencer Desrochers; Steven Eugene Turner (BCICTS, 2024)