BIST controlled variable sense amp timing for 90nm embedded SRAM. - Ciaran J. Brennan; Steven Eustis; John Goss; A. Humphrey; Michael Ouellette; Jeremy Rowland; Michael Fragano (CICC, 2004)

An embedded read only memory architecture with a complementary and two interchangeable power/performance design points. - Steven Eustis (SoCC, 2004)