Timing-Abstract Circuit Design in Transaction-Level Verilog. - Steven F. Hoover (ICCD, 2017)

Top-Down Transaction-Level Design with TL-Verilog. - Steven F. Hoover; Ahmed Salman (CoRR, 2018)

Formally Verifying WARP-V, an Open-Source TL-Verilog RISC-V Core Generator. - Steven F. Hoover; Ákos Hadnagy (CoRR, 2018)