Bridge: A Versatile Behavioral Synthesis System. - Chia-Jeng Tseng; Ruey-Sing Wei; Steven G. Rothweiler; Michael M. Tong; Ajoy K. Bose (DAC, 1988)

BECOME: Behavior Level Circuit Synthesis Based on Structure Mapping. - Ruey-Sing Wei; Steven G. Rothweiler; Jing-Yang Jou (DAC, 1988)

Mind: a module binder for high level synthesis. - Chia-Jeng Tseng; Steven G. Rothweiler; Shailesh Sutarwala; Ajit M. Prabhu (ICCD, 1989)

Performance optimization of sequential circuits by eliminating retiming bottlenecks. - Sujit Dey; Miodrag Potkonjak; Steven G. Rothweiler (ICCAD, 1992)

Sequential Circuit Delay optimization Using Global Path Delays. - Srimat T. Chakradhar; Sujit Dey; Miodrag Potkonjak; Steven G. Rothweiler (DAC, 1993)

A transitive closure algorithm for test generation. - Srimat T. Chakradhar; Vishwani D. Agrawal; Steven G. Rothweiler (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

Redundancy Removal and Test Generation for Circuits with Non-Boolean Primitives. - Srimat T. Chakradhar; Steven G. Rothweiler (VTS, 1995)

Deriving Signal Constraints to Accelerate Sequential Test Generation. - Srimat T. Chakradhar; Vijay Gangaram; Steven G. Rothweiler (VLSI Design, 1997)

Redundancy removal and test generation for circuits with non-Boolean primitives. - Srimat T. Chakradhar; Steven G. Rothweiler; Vishwani D. Agrawal (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)