Dealing with Inductance in High-Speed Chip Design. - Phillip J. Restle; Albert E. Ruehli; Steven G. Walker (DAC, 1999)

Multi-GHz interconnect effects in microprocessors. - Phillip J. Restle; Albert E. Ruehli; Steven G. Walker (ISPD, 2001)

Full-wave PEEC time-domain method for the modeling of on-chipinterconnects. - Phillip J. Restle; Albert E. Ruehli; Steven G. Walker; George Papadopoulos (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

First-order incremental block-based statistical timing analysis. - Chandramouli Visweswariah; K. Ravindran; Kerim Kalafala; Steven G. Walker; S. Narayan (DAC, 2004)

First-Order Incremental Block-Based Statistical Timing Analysis. - Chandramouli Visweswariah; K. Ravindran; Kerim Kalafala; Steven G. Walker; S. Narayan; Daniel K. Beece; Jeff Piaget; Natesan Venkateswaran; Jeffrey G. Hemmett (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

An Integrated CAD Methodology for Evaluating MOSFET and Parasitic Extraction Models and Variability. - Koushik K. Das; Steven G. Walker; Manjul Bhushan (Proc. IEEE, 2007)