The evolution of IBM CMOS DRAM technology. - Eric Adler; John K. DeBrosse; Stephen F. Geissler; Steven J. Holmes; Mark D. Jaffe; Jeffrey B. Johnson; Charles W. Koburger III; Jerome B. Lasky; Brian Lloyd; Glen L. Miles; James S. Nakos; Wendell P. Noble Jr.; et al. (IBM J. Res. Dev., 1995)

Overview of gate linewidth control in the manufacture of CMOS logic chips. - Donald G. Chesebro; James W. Adkisson; Lyman R. Clark; Steven N. Eslinger; Margaret A. Faucher; Steven J. Holmes; Raymond P. Mallette; Edward J. Nowak; Edward W. Sengle; Steven H. Voldman; Thomas W. Weeks (IBM J. Res. Dev., 1995)

The state of the art of electrostatic discharge protection: physics, technology, circuits, design, simulation, and scaling. - Steven H. Voldman (IEEE J. Solid State Circuits, 1999)

A strategy for characterization and evaluation of ESD robustness of CMOS semiconductor technologies. - Steven H. Voldman; W. Anderson; R. Ashton; M. Chaine; Charvaka Duvvury; T. Maloney; E. Worley (Microelectron. Reliab., 2001)

Foundation of rf CMOS and SiGe BiCMOS technologies. - James S. Dunn; David C. Ahlgren; Douglas D. Coolbaugh; Natalie B. Feilchenfeld; Greg G. Freeman; David R. Greenberg; Robert A. Groves; Fernando J. Guarín; Youssef Hammad; Alvin J. Joseph; Louis D. Lanzerotti; Stephen A. St. Onge; et al. (IBM J. Res. Dev., 2003)

Microanalysis and electromigration reliability performance of high current transmission line pulse (TLP) stressed copper interconnects. - Sherry Suat Cheng Khoo; Pee Ya Tan; Steven H. Voldman (Microelectron. Reliab., 2003)

A review of electrostatic discharge (ESD) in advanced semiconductor technology. - Steven H. Voldman (Microelectron. Reliab., 2004)

ESD-Induced Internal Core Device Failure: New Failure Modes in System-on-Chip (SoC) Designs, invited. - Yoon Huh; Peter Bendix; Kyungjin Min; Jau-Wen Chen; Ravindra Narayan; Larry D. Johnson; Steven H. Voldman (IWSOC, 2005)

A review of latchup and electrostatic discharge (ESD) in BiCMOS RF silicon germanium technologies: Part I - ESD. - Steven H. Voldman (Microelectron. Reliab., 2005)

A review of CMOS latchup and electrostatic discharge (ESD) in bipolar complimentary MOSFET (BiCMOS) Silicon Germanium technologies: Part II - Latchup. - Steven H. Voldman (Microelectron. Reliab., 2005)

Electrical Overstress (EOS): Challenges for component and system-level co-design. - Steven H. Voldman (ASICON, 2015)

Computational Simulation of a Field-Induced Charged Board Event Test Bench Using Transient Analysis. - S. Chumpen; S. Pimpakun; S. Plong-Ngooluam; Steven H. Voldman; Chiranut Sa-ngiamsak (IEEE Access, 2023)