Image Quality Issues for High Resolution TFTLCDs. - Steven L. Wright; Robert W. Nywening; Steven E. Millman; James O. Larimer; Jennifer Gille; Jeff Luszcz (CIC, 1998)

A 10.5-in.-diagonal SXGA active-matrix display. - Evan G. Colgan; Paul M. Alt; Robert L. Wisnieff; Peter M. Fryer; Eileen A. Galligan; William S. Graham; Paul F. Greier; Raymond R. Horton; Harold Ifill; Leslie C. Jenkins; Richard A. John; Richard I. Kaufman; et al. (IBM J. Res. Dev., 1998)

Active line repair for thin-film-transistor liquid crystal displays. - Steven L. Wright; Kevin W. Warren; Paul M. Alt; Raymond R. Horton; Chandrasekhar Narayanaswami 001; Paul F. Greier; Manabu Kodate (IBM J. Res. Dev., 1998)

Colorimetric Tolerances of Various Digital Image Displays. - Jason E. Gibson; Mark D. Fairchild; Steven L. Wright (CIC, 2000)

Status of TFTLCD Color and Metrology. - Steven L. Wright; Kenneth C. Ho; Shui-Chih Alan Lien (CIC, 2000)

Multiple images viewable on twisted-nematic mode liquid-crystal displays. - Chai Wah Wu; Gerhard Thompson; Steven L. Wright (IEEE Signal Process. Lett., 2003)

Liquid-crystal displays for medical imaging: a discussion of monochrome versus color. - Steven L. Wright; Ehsan Samei (Image-Guided Procedures, 2004)

Three dimensional silicon integration using fine pitch interconnection, silicon processing and silicon carrier packaging technology. - John U. Knickerbocker; Chirag S. Patel; Paul S. Andry; Cornelia K. Tsang; L. Paivikki Buchwalter; Edmund J. Sprogis; Hua Gan; Raymond R. Horton; Robert J. Polastre; Steven L. Wright; Christian D. Schuster; Christian W. Baks; et al. (CICC, 2005)

Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection. - John U. Knickerbocker; Paul S. Andry; L. Paivikki Buchwalter; Alina Deutsch; Raymond R. Horton; Keith A. Jenkins; Young Hoon Kwark; Gerald McVicker; Chirag S. Patel; Robert J. Polastre; Christian D. Schuster; Arun Sharma; et al. (IBM J. Res. Dev., 2005)

3-D Silicon Integration and Silicon Packaging Technology Using Silicon Through-Vias. - John U. Knickerbocker; Chirag S. Patel; Paul S. Andry; Cornelia K. Tsang; L. Paivikki Buchwalter; Edmund J. Sprogis; Hua Gan; Raymond R. Horton; Robert J. Polastre; Steven L. Wright; John M. Cotte (IEEE J. Solid State Circuits, 2006)

Fabrication and characterization of robust through-silicon vias for silicon-carrier applications. - Paul S. Andry; Cornelia K. Tsang; Bucknell C. Webb; Edmund J. Sprogis; Steven L. Wright; Bing Dang; Dennis G. Manzer (IBM J. Res. Dev., 2008)

3D chip stacking with C4 technology. - Bing Dang; Steven L. Wright; Paul S. Andry; Edmund J. Sprogis; Cornelia K. Tsang; M. John Interrante; Bucknell C. Webb; Robert J. Polastre; Raymond R. Horton; Chirag S. Patel; Arun Sharma; J. Zheng; et al. (IBM J. Res. Dev., 2008)

Three-dimensional silicon integration. - John U. Knickerbocker; Paul S. Andry; Bing Dang; Raymond R. Horton; Mario J. Interrante; Chirag S. Patel; Robert J. Polastre; Katsuyuki Sakuma; Ranjani Sirdeshmukh; Edmund J. Sprogis; Sri M. Sri-Jayantha; Antonio M. Stephens; et al. (IBM J. Res. Dev., 2008)

3D chip-stacking technology with through-silicon vias and low-volume lead-free interconnections. - Katsuyuki Sakuma; Paul S. Andry; Cornelia K. Tsang; Steven L. Wright; Bing Dang; Chirag S. Patel; Bucknell C. Webb; J. Maria; Edmund J. Sprogis; S. K. Kang; Robert J. Polastre; Raymond R. Horton; et al. (IBM J. Res. Dev., 2008)