The first asynchronous microprocessor: the test results. - Alain J. Martin; Steven M. Burns; Tak-Kwan Lee; Drazen Borkovic; Pieter J. Hazewindus (SIGARCH Comput. Archit. News, 1989)

The design of an asynchronous microprocessor. - Alain J. Martin; Steven M. Burns; Tak-Kwan Lee; Drazen Borkovic; Pieter J. Hazewindus (SIGARCH Comput. Archit. News, 1989)

Performance analysis and optimization of asynchronous circuits. - Steven Morgan Burns (1991)

MONTAGNE: An FPL for Synchronous and Asynchronous Circuits. - Scott Hauck; Gaetano Borriello; Steven M. Burns; Carl Ebeling (FPL, 1992)

Practical applications of an efficient time separation of events algorithm. - Henrik Hulgaard; Steven M. Burns; Tod Amon; Gaetano Borriello (ICCAD, 1993)

Bounded delay timing analysis of a class of CSP programs with choice. - Henrik Hulgaard; Steven M. Burns (ASYNC, 1994)

An FPGA for Implementing Asynchronous Circuits. - Scott Hauck; Steven M. Burns; Gaetano Borriello; Carl Ebeling (IEEE Des. Test Comput., 1994)

Efficient Timing Analysis of a Class of Petri Nets. - Henrik Hulgaard; Steven M. Burns (CAV, 1995)

Testing asynchronous circuits: A survey. - Henrik Hulgaard; Steven M. Burns; Gaetano Borriello (Integr., 1995)

An Algorithm for Exact Bounds on the Time Separation of Events in Concurrent Systems. - Henrik Hulgaard; Steven M. Burns; Tod Amon; Gaetano Borriello (IEEE Trans. Computers, 1995)

The Triptych FPGA architecture. - Gaetano Borriello; Carl Ebeling; Scott Hauck; Steven M. Burns (IEEE Trans. Very Large Scale Integr. Syst., 1995)

Placement and routing tools for the Triptych FPGA. - Carl Ebeling; Larry McMurchie; Scott Hauck; Steven M. Burns (IEEE Trans. Very Large Scale Integr. Syst., 1995)

General conditions for the decomposition of state holding elements. - Steven M. Burns (ASYNC, 1996)

Bounded Delay Timing Analysis of a Class of CSP Programs. - Henrik Hulgaard; Steven M. Burns (Formal Methods Syst. Des., 1997)

Model Checking Large Software Specifications. - William Chan 001; Richard J. Anderson 001; Paul Beame; Steve Burns 002; Francesmary Modugno; David Notkin; Jon Damon Reese (IEEE Trans. Software Eng., 1998)

CAD Directions for High Performance Asynchronous Circuits. - Ken S. Stevens; Shai Rotem; Steven M. Burns; Jordi Cortadella; Ran Ginosar; Michael Kishinevsky; Marly Roncken (DAC, 1999)

Synthesis of asynchronous control circuits with automatically generated relative timing assumptions. - Jordi Cortadella; Michael Kishinevsky; Steven M. Burns; Ken S. Stevens (ICCAD, 1999)

Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors. - Tanay Karnik; Yibin Ye; James W. Tschanz; Liqiong Wei; Steven M. Burns; Venkatesh Govindarajulu; Vivek De; Shekhar Borkar (DAC, 2002)

Lazy transition systems and asynchronous circuit synthesis withrelative timing assumptions. - Jordi Cortadella; Michael Kishinevsky; Steven M. Burns; Alex Kondratyev; Luciano Lavagno; Ken S. Stevens; Alexander Taubin; Alexandre Yakovlev (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

Comparative Analysis of Conventional and Statistical Design Techniques. - Steven M. Burns; Mahesh Ketkar; Noel Menezes; Keith A. Bowman; James W. Tschanz; Vivek De (DAC, 2007)

Physical synthesis onto a layout fabric with regular diffusion and polysilicon geometries. - Nikolai Ryzhenko; Steven M. Burns (DAC, 2011)

A trace compression algorithm targeting power estimation of long benchmarks. - Andrey Ayupov; Steven M. Burns (ICCAD, 2011)

Gate sizing and device technology selection algorithms for high-performance industrial designs. - Muhammet Mustafa Ozdal; Steven M. Burns; Jiang Hu (ICCAD, 2011)

Standard cell routing via boolean satisfiability. - Nikolai Ryzhenko; Steven M. Burns (DAC, 2012)

The ISPD-2012 discrete cell sizing contest and benchmark suite. - Muhammet Mustafa Ozdal; Chirayu Amin; Andrey Ayupov; Steven M. Burns; Gustavo R. Wilke; Cheng Zhuo (ISPD, 2012)

Algorithms for Gate Sizing and Device Parameter Selection for High-Performance Designs. - Muhammet Mustafa Ozdal; Steven M. Burns; Jiang Hu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Trace alignment algorithms for offline workload analysis of heterogeneous architectures. - Muhammet Mustafa Ozdal; Aamer Jaleel; Paolo Narváez; Steven M. Burns; Ganapati Srinivasa (ICCAD, 2013)

An improved benchmark suite for the ISPD-2013 discrete cell sizing contest. - Muhammet Mustafa Ozdal; Chirayu Amin; Andrey Ayupov; Steven M. Burns; Gustavo R. Wilke; Cheng Zhuo (ISPD, 2013)

Architectural Requirements for Energy Efficient Execution of Graph Analytics Applications. - Muhammet Mustafa Ozdal; Serif Yesil; Taemin Kim; Andrey Ayupov; Steven M. Burns; Ozcan Ozturk 001 (ICCAD, 2015)

Hardware Accelerator Design for Data Centers. - Serif Yesil; Muhammet Mustafa Ozdal; Taemin Kim; Andrey Ayupov; Steven M. Burns; Ozcan Ozturk 001 (ICCAD, 2015)

Wavelet-Based Trace Alignment Algorithms for Heterogeneous Architectures. - Muhammet Mustafa Ozdal; Aamer Jaleel; Paolo Narváez; Steven M. Burns; Ganapati Srinivasa (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Energy Efficient Architecture for Graph Analytics Accelerators. - Muhammet Mustafa Ozdal; Serif Yesil; Taemin Kim; Andrey Ayupov; John Greth; Steven M. Burns; Özcan Özturk 001 (ISCA, 2016)

Graph Analytics Accelerators for Cognitive Systems. - Muhammet Mustafa Ozdal; Serif Yesil; Taemin Kim; Andrey Ayupov; John Greth; Steven M. Burns; Ozcan Ozturk 001 (IEEE Micro, 2017)

A FPGA Accelerator for Real-Time 3D Non-rigid Registration Using Tree Reweighted Message Passing and Dynamic Markov Random Field Generation. - Michael Barrow; Steven M. Burns; Ryan Kastner (FPL, 2018)

A Template-Based Design Methodology for Graph-Parallel Hardware Accelerators. - Andrey Ayupov; Serif Yesil; Muhammet Mustafa Ozdal; Taemin Kim; Steven M. Burns; Ozcan Ozturk 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

ALIGN: Open-Source Analog Layout Automation from the Ground Up. - Kishor Kunal; Meghna Madhusudan; Arvind K. Sharma; Wenbin Xu; Steven M. Burns; Ramesh Harjani; Jiang Hu; Desmond A. Kirkpatrick; Sachin S. Sapatnekar (DAC, 2019)

Pin Access-Driven Design Rule Clean and DFM Optimized Routing of Standard Cells under Boolean Constraints. - Nikolay Ryzhenko; Steven M. Burns; Anton Sorokin; Mikhail Talalay (ISPD, 2019)

GANA: Graph Convolutional Network Based Automated Netlist Annotation for Analog Circuits. - Kishor Kunal; Tonmoy Dhar; Meghna Madhusudan; Jitesh Poojary; Arvind K. Sharma; Wenbin Xu; Steven M. Burns; Jiang Hu; Ramesh Harjani; Sachin S. Sapatnekar (DATE, 2020)

The ALIGN Open-Source Analog Layout Generator: v1.0 and Beyond (Invited talk). - Tonmoy Dhar; Kishor Kunal; Yaguang Li; Yishuang Lin; Meghna Madhusudan; Jitesh Poojary; Arvind K. Sharma; Steven M. Burns; Ramesh Harjani; Jiang Hu; Parijat Mukherjee; Soner Yaldiz; et al. (ICCAD, 2020)

Learning from Experience: Applying ML to Analog Circuit Design. - Kishor Kunal; Tonmoy Dhar; Yaguang Li; Meghna Madhusudan; Jitesh Poojary; Arvind K. Sharma; Wenbin Xu; Steven M. Burns; Ramesh Harjani; Jiang Hu; Parijat Mukherjee; Sachin S. Sapatnekar (ISPD, 2020)

Common-Centroid Layouts for Analog Circuits: Advantages and Limitations. - Arvind K. Sharma; Meghna Madhusudan; Steven M. Burns; Parijat Mukherjee; Soner Yaldiz; Ramesh Harjani; Sachin S. Sapatnekar (DATE, 2021)

Performance-Aware Common-Centroid Placement and Routing of Transistor Arrays in Analog Circuits. - Arvind K. Sharma; Meghna Madhusudan; Steven M. Burns; Soner Yaldiz; Parijat Mukherjee; Ramesh Harjani; Sachin S. Sapatnekar (ICCAD, 2021)

Machine Learning Techniques in Analog Layout Automation. - Tonmoy Dhar; Kishor Kunal; Yaguang Li; Yishuang Lin; Meghna Madhusudan; Jitesh Poojary; Arvind K. Sharma; Steven M. Burns; Ramesh Harjani; Jiang Hu; Parijat Mukherjee; Soner Yaldiz; et al. (ISPD, 2021)

A Highly Configurable Hardware/Software Stack for DNN Inference Acceleration. - Suvadeep Banerjee; Steve Burns 002; Pasquale Cocchini; Abhijit Davare; Shweta Jain 005; Desmond Kirkpatrick; Anton Sorokin; Jin Yang 006; Zhenkun Yang (CoRR, 2021)

ALIGN: A System for Automating Analog Layout. - Tonmoy Dhar; Kishor Kunal; Yaguang Li; Meghna Madhusudan; Jitesh Poojary; Arvind K. Sharma; Wenbin Xu; Steven M. Burns; Ramesh Harjani; Jiang Hu; Desmond A. Kirkpatrick; Parijat Mukherjee; et al. (IEEE Des. Test, 2021)

A Charge Flow Formulation for Guiding Analog/Mixed-Signal Placement. - Tonmoy Dhar; Ramprasath S 001; Jitesh Poojary; Soner Yaldiz; Steven M. Burns; Ramesh Harjani; Sachin S. Sapatnekar (DATE, 2022)

Analog/Mixed-Signal Layout Optimization using Optimal Well Taps. - Ramprasath S 001; Meghna Madhusudan; Arvind K. Sharma; Jitesh Poojary; Soner Yaldiz; Ramesh Harjani; Steven M. Burns; Sachin S. Sapatnekar (ISPD, 2022)

Reusing GEMM Hardware for Efficient Execution of Depthwise Separable Convolution on ASIC-Based DNN Accelerators. - Susmita Dey Manasi; Suvadeep Banerjee; Abhijit Davare; Anton A. Sorokin; Steven M. Burns; Desmond A. Kirkpatrick; Sachin S. Sapatnekar (ASP-DAC, 2023)

GNN-Based Hierarchical Annotation for Analog Circuits. - Kishor Kunal; Tonmoy Dhar; Meghna Madhusudan; Jitesh Poojary; Arvind K. Sharma; Wenbin Xu; Steven M. Burns; Jiang Hu; Ramesh Harjani; Sachin S. Sapatnekar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

A Generalized Methodology for Well Island Generation and Well-tap Insertion in Analog/Mixed-signal Layouts. - Ramprasath Srinivasa Gopalakrishnan; Meghna Madhusudan; Arvind K. Sharma; Jitesh Poojary; Soner Yaldiz; Ramesh Harjani; Steven M. Burns; Sachin S. Sapatnekar (ACM Trans. Design Autom. Electr. Syst., 2023)

Constructive Place-and-Route for FinFET-Based Transistor Arrays in Analog Circuits Under Nonlinear Gradients. - Arvind K. Sharma; Meghna Madhusudan; Steven M. Burns; Soner Yaldiz; Parijat Mukherjee; Ramesh Harjani; Sachin S. Sapatnekar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)