A performance counter architecture for computing accurate CPI components. - Stijn Eyerman; Lieven Eeckhout; Tejas Karkhanis; James E. Smith 001 (ASPLOS, 2006)

Efficient design space exploration of high performance embedded out-of-order processors. - Stijn Eyerman; Lieven Eeckhout; Koen De Bosschere (DATE, 2006)

Characterizing the branch misprediction penalty. - Stijn Eyerman; James E. Smith 001; Lieven Eeckhout (ISPASS, 2006)

Studying Compiler-Microarchitecture Interactions through Interval Analysis. - Stijn Eyerman; Lieven Eeckhout; James E. Smith 001 (PACT, 2007)

A Memory-Level Parallelism Aware Fetch Policy for SMT Processors. - Stijn Eyerman; Lieven Eeckhout (HPCA, 2007)

A Top-Down Approach to Architecting CPI Component Performance Counters. - Stijn Eyerman; Lieven Eeckhout; Tejas Karkhanis; James E. Smith 001 (IEEE Micro, 2007)

Studying Compiler Optimizations on Superscalar Processors Through Interval Analysis. - Stijn Eyerman; Lieven Eeckhout; James E. Smith 001 (HiPEAC, 2008)

System-Level Performance Metrics for Multiprogram Workloads. - Stijn Eyerman; Lieven Eeckhout (IEEE Micro, 2008)

Per-thread cycle accounting in SMT processors. - Stijn Eyerman; Lieven Eeckhout (ASPLOS, 2009)

MLP-Aware Runahead Threads in a Simultaneous Multithreading Processor. - Kenzo Van Craeynest; Stijn Eyerman; Lieven Eeckhout (HiPEAC, 2009)

Memory-level parallelism aware fetch policies for simultaneous multithreading processors. - Stijn Eyerman; Lieven Eeckhout (ACM Trans. Archit. Code Optim., 2009)

A mechanistic performance model for superscalar out-of-order processors. - Stijn Eyerman; Lieven Eeckhout; Tejas Karkhanis; James E. Smith 001 (ACM Trans. Comput. Syst., 2009)

Probabilistic job symbiosis modeling for SMT processor scheduling. - Stijn Eyerman; Lieven Eeckhout (ASPLOS, 2010)

Interval simulation: Raising the level of abstraction in architectural simulation. - Davy Genbrugge; Stijn Eyerman; Lieven Eeckhout (HPCA, 2010)

Modeling critical sections in Amdahl's law and its implications for multicore design. - Stijn Eyerman; Lieven Eeckhout (ISCA, 2010)

Per-Thread Cycle Accounting. - Stijn Eyerman; Lieven Eeckhout (IEEE Micro, 2010)

A Counter Architecture for Online DVFS Profitability Estimation. - Stijn Eyerman; Lieven Eeckhout (IEEE Trans. Computers, 2010)

Mechanistic-empirical processor performance modeling for constructing CPI stacks on real hardware. - Stijn Eyerman; Kenneth Hoste; Lieven Eeckhout (ISPASS, 2011)

How sensitive is processor customization to the workload's input datasets? - Maximilien Breughe; Zheng Li; Yang Chen; Stijn Eyerman; Olivier Temam; Chengyong Wu; Lieven Eeckhout (SASP, 2011)

Fine-grained DVFS using on-chip regulators. - Stijn Eyerman; Lieven Eeckhout (ACM Trans. Archit. Code Optim., 2011)

An efficient CPI stack counter architecture for superscalar processors. - Osman Allam; Stijn Eyerman; Lieven Eeckhout (ACM Great Lakes Symposium on VLSI, 2012)

A first-order mechanistic model for architectural vulnerability factor. - Arun A. Nair; Stijn Eyerman; Lieven Eeckhout; Lizy Kurian John (ISCA, 2012)

A mechanistic performance model for superscalar in-order processors. - Maximilien Breughe; Stijn Eyerman; Lieven Eeckhout (ISPASS, 2012)

Speedup stacks: Identifying scaling bottlenecks in multi-threaded applications. - Stijn Eyerman; Kristof Du Bois; Lieven Eeckhout (ISPASS, 2012)

Probabilistic modeling for job symbiosis scheduling on SMT processors. - Stijn Eyerman; Lieven Eeckhout (ACM Trans. Archit. Code Optim., 2012)

Criticality stacks: identifying critical threads in parallel programs using synchronization behavior. - Kristof Du Bois; Stijn Eyerman; Jennifer B. Sartor; Lieven Eeckhout (ISCA, 2013)

Bottle graphs: visualizing scalability bottlenecks in multi-threaded applications. - Kristof Du Bois; Jennifer B. Sartor; Stijn Eyerman; Lieven Eeckhout (OOPSLA, 2013)

Per-thread cycle accounting in multicore processors. - Kristof Du Bois; Stijn Eyerman; Lieven Eeckhout (ACM Trans. Archit. Code Optim., 2013)

The benefit of SMT in the multi-core era: flexibility towards degrees of thread-level parallelism. - Stijn Eyerman; Lieven Eeckhout (ASPLOS, 2014)

Restating the Case for Weighted-IPC Metrics to Evaluate Multiprogram Workload Performance. - Stijn Eyerman; Lieven Eeckhout (IEEE Comput. Archit. Lett., 2014)

Mechanistic Analytical Modeling of Superscalar In-Order Processor Performance. - Maximilien Breughe; Stijn Eyerman; Lieven Eeckhout (ACM Trans. Archit. Code Optim., 2014)

An Evaluation of High-Level Mechanistic Core Models. - Trevor E. Carlson; Wim Heirman; Stijn Eyerman; Ibrahim Hur; Lieven Eeckhout (ACM Trans. Archit. Code Optim., 2014)

Multiprogram Throughput Metrics: A Systematic Approach. - Stijn Eyerman; Pierre Michaud; Wouter Rogiest (ACM Trans. Archit. Code Optim., 2014)

Revisiting symbiotic job scheduling. - Stijn Eyerman; Pierre Michaud; Wouter Rogiest (ISPASS, 2015)

Micro-architecture independent branch behavior characterization. - Sander De Pestel; Stijn Eyerman; Lieven Eeckhout (ISPASS, 2015)

Micro-architecture independent analytical processor performance and power modeling. - Sam Van den Steen; Sander De Pestel; Moncef Mechri; Stijn Eyerman; Trevor E. Carlson; David Black-Schaffer; Erik Hagersten; Lieven Eeckhout (ISPASS, 2015)

Mechanistic Modeling of Architectural Vulnerability Factor. - Arun Arvind Nair; Stijn Eyerman; Jian Chen 030; Lizy Kurian John; Lieven Eeckhout (ACM Trans. Comput. Syst., 2015)

Symbiotic job scheduling on the IBM POWER8. - Josué Feliu; Stijn Eyerman; Julio Sahuquillo; Salvador Petit (HPCA, 2016)

Maximizing Heterogeneous Processor Performance Under Power Constraints. - Almutaz Adileh; Stijn Eyerman; Aamer Jaleel; Lieven Eeckhout (ACM Trans. Archit. Code Optim., 2016)

Analytical Processor Performance and Power Modeling Using Micro-Architecture Independent Characteristics. - Sam Van den Steen; Stijn Eyerman; Sander De Pestel; Moncef Mechri; Trevor E. Carlson; David Black-Schaffer; Erik Hagersten; Lieven Eeckhout (IEEE Trans. Computers, 2016)

Reliability-Aware Scheduling on Heterogeneous Multicore Processors. - Ajeya Naithani; Stijn Eyerman; Lieven Eeckhout (HPCA, 2017)

Exploring optimizations on shared-memory platforms for parallel triangle counting algorithms. - Ancy Sarah Tom; Narayanan Sundaram; Nesreen K. Ahmed; Shaden Smith; Stijn Eyerman; Midhunchandra Kodiyath; Ibrahim Hur; Fabrizio Petrini; George Karypis (HPEC, 2017)

Analyzing the scalability of managed language applications with speedup stacks. - Jennifer B. Sartor; Kristof Du Bois; Stijn Eyerman; Lieven Eeckhout (ISPASS, 2017)

Mind The Power Holes: Sifting Operating Points in Power-Limited Heterogeneous Multicores. - Almutaz Adileh; Stijn Eyerman; Aamer Jaleel; Lieven Eeckhout (IEEE Comput. Archit. Lett., 2017)

Linear Branch Entropy: Characterizing and Optimizing Branch Behavior in a Micro-Architecture Independent Way. - Sander De Pestel; Stijn Eyerman; Lieven Eeckhout (IEEE Trans. Computers, 2017)

Improving IBM POWER8 Performance Through Symbiotic Job Scheduling. - Josué Feliu; Stijn Eyerman; Julio Sahuquillo; Salvador Petit; Lieven Eeckhout (IEEE Trans. Parallel Distributed Syst., 2017)

Near-side prefetch throttling: adaptive prefetching for high-performance many-core processors. - Wim Heirman; Kristof Du Bois; Yves Vandriessche; Stijn Eyerman; Ibrahim Hur (PACT, 2018)

Extending the Performance Analysis Tool Box: Multi-stage CPI Stacks and FLOPS Stacks. - Stijn Eyerman; Wim Heirman; Kristof Du Bois; Ibrahim Hur (ISPASS, 2018)

Many-core graph workload analysis. - Stijn Eyerman; Wim Heirman; Kristof Du Bois; Joshua B. Fryman; Ibrahim Hur (SC, 2018)

Multi-Stage CPI Stacks. - Stijn Eyerman; Wim Heirman; Kristof Du Bois; Ibrahim Hur (IEEE Comput. Archit. Lett., 2018)

Optimizing Soft Error Reliability Through Scheduling on Heterogeneous Multicore Processors. - Ajeya Naithani; Stijn Eyerman; Lieven Eeckhout (IEEE Trans. Computers, 2018)

Projecting Performance for PIUMA using Down-Scaled Simulation. - Stijn Eyerman; Wim Heirman; Yigit Demir; Kristof Du Bois; Ibrahim Hur (HPEC, 2020)

Breaking In-Order Branch Miss Recovery. - Stijn Eyerman; Wim Heirman; Sam Van den Steen; Ibrahim Hur (IEEE Comput. Archit. Lett., 2020)

PIUMA: Programmable Integrated Unified Memory Architecture. - Sriram Aananthakrishnan; Nesreen K. Ahmed; Vincent Cavé; Marcelo Cintra; Yigit Demir; Kristof Du Bois; Stijn Eyerman; Joshua B. Fryman; Ivan Ganev; Wim Heirman; Hans-Christian Hoppe; Jason Howard; et al. (CoRR, 2020)

Enabling Branch-Mispredict Level Parallelism by Selectively Flushing Instructions. - Stijn Eyerman; Wim Heirman; Sam Van den Steen; Ibrahim Hur (MICRO, 2021)

Modeling DRAM Timing in Parallel Simulators With Immediate-Response Memory Model. - Stijn Eyerman; Wim Heirman; Ibrahim Hur (IEEE Comput. Archit. Lett., 2021)

RIO: ROB-Centric In-Order Modeling of Out-of-Order Processors. - Wim Heirman; Stijn Eyerman; Kristof Du Bois; Ibrahim Hur (IEEE Comput. Archit. Lett., 2021)

Scale-Model Simulation. - Wenjie Liu; Wim Heirman; Stijn Eyerman; Shoaib Akram 001; Lieven Eeckhout (IEEE Comput. Archit. Lett., 2021)

Automatic Sublining for Efficient Sparse Memory Accesses. - Wim Heirman; Stijn Eyerman; Kristof Du Bois; Ibrahim Hur (ACM Trans. Archit. Code Optim., 2021)

DRAM Bandwidth and Latency Stacks: Visualizing DRAM Bottlenecks. - Stijn Eyerman; Wim Heirman; Ibrahim Hur (ISPASS, 2022)

Scale-Model Architectural Simulation. - Wenjie Liu; Wim Heirman; Stijn Eyerman; Shoaib Akram 001; Lieven Eeckhout (ISPASS, 2022)

Efficient Asynchronous RPC Calls for Microservices: DeathStarBench Study. - Stijn Eyerman; Ibrahim Hur (CoRR, 2022)

Execution Time Estimation of Multithreaded Programs With Critical Sections. - Dimitri Kagaris; Sourav Dutta; Stijn Eyerman (IEEE Trans. Parallel Distributed Syst., 2022)

Simulating Wrong-Path Instructions in Decoupled Functional-First Simulation. - Stijn Eyerman; Sam Van den Steen; Wim Heirman; Ibrahim Hur (ISPASS, 2023)

The Intel Programmable and Integrated Unified Memory Architecture Graph Analytics Processor. - Sriram Aananthakrishnan; Shamsul Abedin; Vincent Cavé; Fabio Checconi; Kristof Du Bois; Stijn Eyerman; Joshua B. Fryman; Wim Heirman; Jason Howard; Ibrahim Hur; Samkit Jain; Marek M. Landowski; et al. (IEEE Micro, 2023)

Message from the Program Chairs; ISPASS 2024. - Wim Heirman; Stijn Eyerman (ISPASS, 2024)

Accurate and Scalable Many-Node Simulation. - Stijn Eyerman; Wim Heirman; Kristof Du Bois; Ibrahim Hur (CoRR, 2024)

Multi-Core Aware Evaluation of Prefetchers. - Martí Torrents; Paul Caheny; Stijn Eyerman; Wim Heirman (ISPASS, 2025)

DECA: A Near-Core LLM Decompression Accelerator Supporting Out-of-Order Invocation. - Gerasimos Gerogiannis; Stijn Eyerman; Evangelos Georganas; Wim Heirman; Josep Torrellas (CoRR, 2025)