FPGA test time reduction through a novel interconnect testing scheme. - Stuart McCracken; Zeljko Zilic (FPGA, 2002)

Design for Testability of FPGA Blocks. - Stuart McCracken; Zeljko Zilic (ISQED, 2004)

A 6.5Mb/s to 11.3Gb/s continuous-rate clock and data recovery. - Jack Kenney; Terry Chen; Larry DeVito; Declan Dalton; Stuart McCracken; Richard Soenneker; Ward S. Titus; Todd S. Weigandt (CICC, 2014)

24.8 A 12GS/s 9b 16× Time-Interleaved SAR ADC in 16nm FinFET. - Junhua Shen; Wei-Hung Chen; Efram Burlingame; Stephen Weinreich; Michael Elliott; Stuart McCracken; Jack Kenney; Janet Brunsilius; Anil Korkmaz; Enrique Alvarez-Fontecilla; Nevena Rakuljic; Ushma Mehta; et al. (ISSCC, 2025)