Background calibration of integrator leakage in discrete-time delta-sigma modulators. - Su-Hao Wu; Jieh-Tsorng Wu (NEWCAS, 2013)

A 81-dB Dynamic Range 16-MHz Bandwidth ΔΣ Modulator Using Background Calibration. - Su-Hao Wu; Jieh-Tsorng Wu (IEEE J. Solid State Circuits, 2013)

15.6 A 160MHz-BW 72dB-DR 40mW continuous-time ΔΣ modulator in 16nm CMOS with analog ISI-reduction technique. - Su-Hao Wu; Tsung-Kai Kao; Zwei-Mei Lee; Ping Chen; Jui-Yuan Tsai (ISSCC, 2016)

An Amplifier-Less Calibration-Free SAR ADC Achieving >100dB SNDR for Multi-Channel ECG Acquisition with 667mVpp Linear Input Range. - Wei-Hsiang Huang; Su-Hao Wu; Zhi-Xin Chen; Yun-Shiang Shu (VLSI Circuits, 2019)

A 71. 4dB SNDR 30MHz BW Continuous-Time Delta-sigma Modulator Using a Time-Interleaved Noise-Shaping Quantizer in 12-nm CMOS. - Chan-Hsiang Weng; Tzu-An Wei; Hung-Yi Hsieh; Su-Hao Wu; Ting-Yang Wang (VLSI Circuits, 2019)

26.1 A 4.5mm2 Multimodal Biosensing SoC for PPG, ECG, BIOZ and GSR Acquisition in Consumer Wearable Devices. - Yun-Shiang Shu; Zhi-Xin Chen; Yu-Hong Lin; Su-Hao Wu; Wei-Hsiang Huang; Albert Yen-Chih Chiou; Chang-Yang Huang; Hung-Yi Hsieh; Fan-Wei Liao; Teng-Feng Zou; Ping Chen (ISSCC, 2020)

9.1 A Current-Sensing Front-End Realized by A Continuous-Time Incremental ADC with 12b SAR Quantizer and Reset-Then-Open Resistive DAC Achieving 140dB DR and 8ppm INL at 4kS/s. - Su-Hao Wu; Yun-Shiang Shu; Albert Yen-Chih Chiou; Wei-Hsiang Huang; Zhi-Xin Chen; Hung-Yi Hsieh (ISSCC, 2020)