Fast design approach for implementing the approximate squaring function. - Ming-Hwa Sheu; Su-Hon Lin (APCCAS (2), 2002)

Fast compensative design approach for the approximate squaring function. - Ming-Hwa Sheu; Su-Hon Lin (IEEE J. Solid State Circuits, 2002)

An efficient VLSI design for a residue to binary converter for general balance moduli (2n-3, 2n+1, 2n-1, 2n+3). - Ming-Hwa Sheu; Su-Hon Lin; Chichyang Chen; Shyue-Wen Yang (IEEE Trans. Circuits Syst. II Express Briefs, 2004)

Efficient VLSI Design for RNS Reverse Converter Based on New Moduli Set (2n-1, 2n+1, 22n+1). - Su-Hon Lin; Ming-Hwa Sheu; Jing-Shiun Lin; Wen-Tsai Sheu (APCCAS, 2006)

Efficient VLSI Design of Modulo 2n-1 Adder Using Hybrid Carry Selection. - Su-Hon Lin; Ming-Hwa Sheu; Kuang-Hui Wang; Jun-Jie Zhu; Si-Ying Chen (SiPS, 2007)

Area-time-power efficient VLSI design for residue-to-binary converter based on moduli set (2n, 2n+1-1, 2n-1). - Su-Hon Lin; Ming-Hwa Sheu; Chao-Hsiang Wang; Yuan-Ching Kuo (APCCAS, 2008)

Area-Time Efficient Modulo 2n - 1 Adder Design Using Hybrid Carry Selection. - Su-Hon Lin; Ming-Hwa Sheu (IEICE Trans. Inf. Syst., 2008)

Efficient VLSI Design of Residue-to-Binary Converter for the Moduli Set (2n, 2n+1 - 1, 2n - 1). - Su-Hon Lin; Ming-Hwa Sheu; Chao-Hsiang Wang (IEICE Trans. Inf. Syst., 2008)

VLSI Design of Diminished-One Modulo 2n+1 Adder Using Circular Carry Selection. - Su-Hon Lin; Ming-Hwa Sheu (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

Efficient VLSI Design of a Reverse RNS Converter for New Flexible 4-Moduli Set (2p+k, 2p+1, 2p-1, 22p+1). - Yuan-Ching Kuo; Su-Hon Lin; Ming-Hwa Sheu; Jia-You Wu; Peng-Siang Wang (ISCAS, 2009)

Efficient Reverse Converter Design for New Adaptable Four-Moduli Set {2n + k, 2n + 1, 2n - 1, 22n + 1}. - Ming-Hwa Sheu; Yuan-Ching Kuo; Su-Hon Lin; Siang-Min Siao (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)