Su-Hyun Han

Orcid: 0000-0003-4879-0657

Affiliations:
  • Ulsan National Institute of Science and Technology, 2School of Electrical and Computer Engineering, Ulsan, Korea


According to our database1, Su-Hyun Han authored at least 8 papers between 2018 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Bibliography

2024
6.7 A 160×120 Flash LiDAR Sensor with Fully Analog-Assisted In- Pixel Histogramming TDC Based on Self-Referenced SAR ADC.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2022
An 80 × 60 Flash LiDAR Sensor With In-Pixel Delta-Intensity Quaternary Search Histogramming TDC.
IEEE J. Solid State Circuits, 2022

A 3.8-µW 1.5-NEF 15-GΩ Total Input Impedance Chopper Stabilized Amplifier With Auto-Calibrated Dual Positive Feedback in 110-nm CMOS.
IEEE J. Solid State Circuits, 2022

A 100×80 CMOS Flash LiDAR Sensor with 0.0011mm<sup>2</sup> In-Pixel Histogramming TDC Based on Analog Counter and Self-Calibrated Single-Slope ADC.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2021
A 3.8-μW/Ch, 15-GΩ Total Input Impedance Chopper Stabilized Amplifier with Dual Positive Feedback Loops and Auto-calibration Scheme.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

2020
A Real-Time Depth of Anesthesia Monitoring System Based on Deep Neural Network With Large EDO Tolerant EEG Analog Front-End.
IEEE Trans. Biomed. Circuits Syst., 2020

2019
A Sub-µW/Ch Analog Front-End for Δ-Neural Recording With Spike-Driven Data Compression.
IEEE Trans. Biomed. Circuits Syst., 2019

2018
A 4.86 µW/Channel Fully Differential Multi-Channel Neural Recording System.
Proceedings of the International SoC Design Conference, 2018


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