Realizing Cycle Accurate Processor Memory Simulation via Interface Abstraction. - Su Myat Min; Jorgen Peddersen; Sri Parameswaran (VLSI Design, 2011)

RExCache: Rapid exploration of unified last-level cache. - Su Myat Min; Haris Javaid; Sri Parameswaran (ASP-DAC, 2013)

XDRA: exploration and optimization of last-level cache for energy reduction in DDR DRAMs. - Su Myat Min; Haris Javaid; Sri Parameswaran (DAC, 2013)

A case study on exploration of last-level cache for energy reduction in DDR3 DRAM. - Su Myat Min; Haris Javaid; Aleksandar Ignjatovic; Sri Parameswaran (MECO, 2013)

Energy-efficient low power optimisation methodologies for DRAM memory of embedded system. - Su Myat Min Shwe (2013)

FALCON: A Framework for HierarchicAL Computation of Metrics for CompONent-Based Parameterized SoCs. - Haris Javaid; Yusuke Yachide; Su Myat Min Shwe; Haseeb Bokhari; Sri Parameswaran (DAC, 2014)

RAPITIMATE: Rapid performance estimation of pipelined processing systems containing shared memory. - Su Myat Min Shwe; Kapil Batra; Yusuke Yachide; Jorgen Peddersen; Sri Parameswaran (ICCD, 2015)