A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW. - Seung-Jun Bae; Young-Soo Sohn; Tae-Young Oh; Si-Hong Kim; Yun-Seok Yang; Dae-Hyun Kim 003; Sang-Hyup Kwak; Ho-Seok Seol; Chang-Ho Shin; Min-Sang Park; Gong-Heom Han; Byeong-Cheol Kim; et al. (ISSCC, 2011)

25.1 A 3.2Gb/s/pin 8Gb 1.0V LPDDR4 SDRAM with integrated ECC engine for sub-1V DRAM core operation. - Tae-Young Oh; Hoeju Chung; Young-Chul Cho; Jang-Woo Ryu; Kiwon Lee; Changyoung Lee; Jin-Il Lee; Hyoung-Joo Kim 002; Min-Soo Jang; Gong-Heum Han; Kihan Kim; Daesik Moon; et al. (ISSCC, 2014)

A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation. - Tae-Young Oh; Hoeju Chung; Jun-Young Park; Ki-Won Lee; Seung-Hoon Oh; Su-Yeon Doo; Hyoung-Joo Kim 002; ChangYong Lee; Hye-Ran Kim; Jong-Ho Lee; Jin-Il Lee; Kyung-Soo Ha; et al. (IEEE J. Solid State Circuits, 2015)

23.4 An extremely low-standby-power 3.733Gb/s/pin 2Gb LPDDR4 SDRAM for wearable devices. - Hye-Jung Kwon; Eunsung Seo; ChangYong Lee; Young-Hun Seo; Gong-Heum Han; Hye-Ran Kim; Jong-Ho Lee; Min-Su Jang; Sung-Geun Do; Seung-Hyun Cho; Jae-Koo Park; Su-Yeon Doo; et al. (ISSCC, 2017)

A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking. - Young-Ju Kim 001; Hye-Jung Kwon; Su-Yeon Doo; Yoon-Joo Eom; Young-Sik Kim; Min-Su Ahn; Yong-Hun Kim; Sang-Hoon Jung; Sung-Geun Do; Chang-Yong Lee; Jae-Sung Kim; Dong-Seok Kang; et al. (ISSCC, 2018)

A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking. - Young-Ju Kim 001; Hye-Jung Kwon; Su-Yeon Doo; Min-Su Ahn; Yong-Hun Kim; Yong Jae Lee; Dong-Seok Kang; Sung-Geun Do; Chang-Yong Lee; Gun-hee Cho; Jae-Koo Park; Jae-Sung Kim; et al. (IEEE J. Solid State Circuits, 2019)

22.2 An 8.5Gb/s/pin 12Gb-LPDDR5 SDRAM with a Hybrid-Bank Architecture using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a 2nd generation 10nm DRAM Process. - Hyung-Joon Chi; Chang-Kyo Lee; Junghwan Park; Jin-Seok Heo; Jaehoon Jung; Dongkeon Lee; Dae-Hyun Kim 003; Dukha Park; Kihan Kim; Sang-Yun Kim 001; Jinsol Park; Hyunyoon Cho; et al. (ISSCC, 2020)

Dynamic Power Reduction of TCAM Using Selective Precharging of Match Lines. - Su-Yeon Doo; Kee-Won Kwon (IEEE Big Data, 2022)