A 4-Gb/s/pin low-power memory I/O interface using 4-level simultaneous bi-directional signaling. - Jin-Hyun Kim; Sua Kim; Woo-Seop Kim; Jung-Hwan Choi; Hong-Sun Hwang; Changhyun Kim; Suki Kim (IEEE J. Solid State Circuits, 2005)

A 31 ns Random Cycle VCAT-Based 4F 2 DRAM With Manufacturability and Enhanced Cell Efficiency. - Ki-Whan Song; Jinyoung Kim; Jae-Man Yoon; Sua Kim; Huijung Kim; Hyun-Woo Chung; Hyungi Kim; Kanguk Kim; Hwan-Wook Park; Hyun Chul Kang; Nam-Kyun Tak; Dukha Park; et al. (IEEE J. Solid State Circuits, 2010)

A 12-28 Gb/s Temperature Compensated PAM-4 Transmitter with 7B4Q Maximum Transition Avoidance and Fractional-Spaced FFE. - Sua Kim; Jin-Ku Kang (ISOCC, 2024)