A Design Methodology for a Fully Synthesized High Speed DSP Core in a Deep Sub-Micron Technology. - Avinash K. Gautam; Jagdish C. Rao; Karthikeyan Madathil; Vilesh Shah; H. Udayakumar; Amitabh Menon; Subash Chandar G. (ICCD, 1999)

A Framework for Cost vs. Performance Tradeoffs in the Design of Digital Signal Processor Cores. - Karthikeyan Madathil; Jagdish C. Rao; Subash Chandar G.; Amitabh Menon; Avinash K. Gautam; Amit M. Brahme; H. Udayakumar (VLSI Design, 2000)

Addressing verification bottlenecks of fully synthesized processor cores using equivalence checkers. - Subash Chandar G.; S. Vaideeswaran (ASP-DAC, 2001)

Reset Careabouts in a SoC Design. - Subrangshu Das; Subash Chandar G.; Ashutosh Tiwari (VLSI Design, 2004)

An Effective Framework for Enabling the Reuse of External Soft IP. - Soujanna Sarkar; Subash Chandar G. (DSD, 2005)

An Effective IP Reuse Methodology for Quality System-on-Chip Design. - Soujanna Sarkar; Sanjay Shinde; Subash Chandar G. (SoC, 2005)

Effective IP reuse for high quality SOC design. - Soujanna Sarkar; Subash Chandar G.; Sanjay Shinde (SoCC, 2005)

Area and Power Reduction of Embedded DSP Systems using Instruction Compression and Re-configurable Encoding. - Subash Chandar G.; Mahesh Mehendale; R. Govindarajan (J. VLSI Signal Process., 2006)