Scan Synthesis for One-Hot Signals. - Subhasish Mitra; LaNae J. Avra; Edward J. McCluskey (ITC, 1997)

A design diversity metric and reliability analysis for redundant systems. - Subhasish Mitra; Nirmal R. Saxena; Edward J. McCluskey (ITC, 1999)

An output encoding problem and a solution technique. - Subhasish Mitra; LaNae J. Avra; Edward J. McCluskey (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

DUDES: A Fault Abstraction and Collapsing Framework for Asynchronous Circuits. - Philip P. Shirvani; Subhasish Mitra; Jo C. Ebergen; Marly Roncken (ASYNC, 2000)

Combinational logic synthesis for diversity in duplex systems. - Subhasish Mitra; Edward J. McCluskey (ITC, 2000)

Which concurrent error detection scheme to choose ? - Subhasish Mitra; Edward J. McCluskey (ITC, 2000)

Word Voter: A New Voter Design for Triple Modular Redundant Systems. - Subhasish Mitra; Edward J. McCluskey (VTS, 2000)

Fault Escapes in Duplex Systems. - Subhasish Mitra; Nirmal R. Saxena; Edward J. McCluskey (VTS, 2000)

Efficient Multiplexer Synthesis Techniques. - Subhasish Mitra; LaNae J. Avra; Edward J. McCluskey (IEEE Des. Test Comput., 2000)

Dependable Computing and Online Testing in Adaptive and Configurable Systems. - Nirmal R. Saxena; Santiago Fernández-Gomez; Wei-Je Huang; Subhasish Mitra; Shu-Yi Yu; Edward J. McCluskey (IEEE Des. Test Comput., 2000)

Common-mode failures in redundant VLSI systems: a survey. - Subhasish Mitra; Nirmal R. Saxena; Edward J. McCluskey (IEEE Trans. Reliab., 2000)

Fast Run-Time Fault Location in Dependable FPGA-Based Applications. - Wei-Je Huang; Subhasish Mitra; Edward J. McCluskey (DFT, 2001)

Techniques for Estimation of Design Diversity for Combinational Logic Circuits. - Subhasish Mitra; Nirmal R. Saxena; Edward J. McCluskey (DSN, 2001)

Diversity Techniques for Concurrent Error Detection. - Subhasish Mitra; Edward J. McCluskey (ISQED, 2001)

Design Diversity for Concurrent Error Detection in Sequential Logic Circuts. - Subhasish Mitra; Edward J. McCluskey (VTS, 2001)

Design of Redundant Systems Protected Against Common-Mode Failures. - Subhasish Mitra; Edward J. McCluskey (VTS, 2001)

An Evaluation of Pseudo Random Testing for Detecting Real Defects. - Chao-Wen Tseng; Subhasish Mitra; Edward J. McCluskey; Scott Davidson 001 (VTS, 2001)

Testing Digital Circuits with Constraints. - Ahmad A. Al-Yamani; Subhasish Mitra; Edward J. McCluskey (DFT, 2002)

Dependable Reconfigurable Computing Design Diversity and Self Repair. - Subhasish Mitra; Edward J. McCluskey (Evolvable Hardware, 2002)

X-Compact: An Efficient Response Compaction Technique for Test Cost Reduction. - Subhasish Mitra; Kee Sup Kim (ITC, 2002)

Fault Grading FPGA Interconnect Test Configurations. - Mehdi Baradaran Tahoori; Subhasish Mitra; Shahin Toutounchi; Edward J. McCluskey (ITC, 2002)

Packet-Based Input Test Data Compression Techniques. - Erik H. Volkerink; Ajay Khoche; Subhasish Mitra (ITC, 2002)

Test Vector Compression Using EDA-ATE Synergies. - Ajay Khoche; Erik H. Volkerink; Jochen Rivoir; Subhasish Mitra (VTS, 2002)

Debating the Future of Burn-In. - Edward J. McCluskey; Subhasish Mitra; Bob Madge; Peter C. Maxwell; Phil Nigh; Mike Rodgers (VTS, 2002)

Design for Testability and Testing of IEEE 1149.1 Tap Controller. - Subhasish Mitra; Edward J. McCluskey; Samy Makar (VTS, 2002)

A Design Diversity Metric and Analysis of Redundant Systems. - Subhasish Mitra; Nirmal R. Saxena; Edward J. McCluskey (IEEE Trans. Computers, 2002)

ED4I: Error Detection by Diverse Data and Duplicated Instructions. - Nahmsuk Oh; Subhasish Mitra; Edward J. McCluskey (IEEE Trans. Computers, 2002)

XMAX: X-Tolerant Architecture for MAXimal Test Compression. - Subhasish Mitra; Kee Sup Kim (ICCD, 2003)

H-DFT: A Hybrid DFT Architecture For Low-Cost High Quality Structural Testing. - David M. Wu; Mike Lin; Subhasish Mitra; Kee Sup Kim; Anil Sabbavarapu; Talal Jaber; Pete Johnson; Dale March; Greg Parrish (ITC, 2003)

Bist Reseeding with very few Seeds. - Ahmad A. Al-Yamani; Subhasish Mitra; Edward J. McCluskey (VTS, 2003)

Automatic Configuration Generation for FPGA Interconnect Testing. - Mehdi Baradaran Tahoori; Subhasish Mitra (VTS, 2003)

Efficient Seed Utilization for Reseeding based Compression. - Erik H. Volkerink; Subhasish Mitra (VTS, 2003)

Delay Defect Characteristics and Testing Strategies. - Kee Sup Kim; Subhasish Mitra; Paul G. Ryan (IEEE Des. Test Comput., 2003)

Defect and Fault Tolerance of Reconfigurable Molecular Computing. - Mehdi Baradaran Tahoori; Subhasish Mitra (FCCM, 2004)

Speed Clustering of Integrated Circuits. - Kenneth A. Brand; Erik H. Volkerink; Edward J. McCluskey; Subhasish Mitra (ITC, 2004)

X-Tolerant Signature Analysis. - Subhasish Mitra; Steven S. Lumetta; Michael Mitzenmacher (ITC, 2004)

Interconnect Delay Testing of Designs on Programmable Logic Devices. - Mehdi Baradaran Tahoori; Subhasish Mitra (ITC, 2004)

ELF-Murphy Data on Defects and Test Sets. - Edward J. McCluskey; Ahmad A. Al-Yamani; Chien-Mo James Li; Chao-Wen Tseng; Erik H. Volkerink; François-Fabien Ferhani; Edward Li; Subhasish Mitra (VTS, 2004)

Delay Defect Screening using Process Monitor Structures. - Subhasish Mitra; Erik H. Volkerink; Edward J. McCluskey; Stefan Eichenberger (VTS, 2004)

Conference Reports. - Vladimir Hahanov; Raimund Ubar; Subhasish Mitra (IEEE Des. Test Comput., 2004)

Reconfigurable Architecture for Autonomous Self-Repair. - Subhasish Mitra; Wei-Je Huang; Nirmal R. Saxena; Shu-Yi Yu; Edward J. McCluskey (IEEE Des. Test Comput., 2004)

Efficient Design Diversity Estimation for Combinational Circuits. - Subhasish Mitra; Nirmal R. Saxena; Edward J. McCluskey (IEEE Trans. Computers, 2004)

X-compact: an efficient response compaction technique. - Subhasish Mitra; Kee Sup Kim (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Techniques and algorithms for fault grading of FPGA interconnect test configurations. - Mehdi Baradaran Tahoori; Subhasish Mitra (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Robust platform design in advanced VLSI technologies. - David J. Leavins; Kee Sup Kim; Subhasish Mitra; Eddie J. Rodriguez (CICC, 2005)

Logic soft errors in sub-65nm technologies design and CAD challenges. - Subhasish Mitra; Tanay Karnik; Norbert Seifert; Ming Zhang (DAC, 2005)

Response compaction with any number of unknowns using a new LFSR architecture. - Erik H. Volkerink; Subhasish Mitra (DAC, 2005)

DFT Assisted Built-In Soft Error Resilience. - T. M. Mak; Subhasish Mitra; Ming Zhang (IOLTS, 2005)

Gate exhaustive testing. - Kyoung Youn Cho; Subhasish Mitra; Edward J. McCluskey (ITC, 2005)

Logic soft errors: a major barrier to robust platform design. - Subhasish Mitra; Ming Zhang 017; T. M. Mak; Norbert Seifert; Victor Zia; Kee Sup Kim (ITC, 2005)

Enabling yield analysis with X-compact. - Zoran Stanojevic; Ruifeng Guo; Subhasish Mitra; Srikanth Venkataraman (ITC, 2005)

Testing Nanometer Digital Integration Circuits: Myths, Reality and the Road Ahead. - R. D. (Shawn) Blanton; Subhasish Mitra (VLSI Design, 2005)

Subhasish Mitra, Norbert Seifert, Ming Zhang, Quan Shi, Kee Sup Kim. - Subhasish Mitra; Norbert Seifert; Ming Zhang 017; Quan Shi; Kee Sup Kim (Computer, 2005)

X-Tolerant Test Response Compaction. - Subhasish Mitra; Steven S. Lumetta; Michael Mitzenmacher; Nishant Patil (IEEE Des. Test Comput., 2005)

Recent Advances and New Avenues in Hardware-Level Reliability Support. - Ravishankar K. Iyer; Nithin Nakka; Zbigniew Kalbarczyk; Subhasish Mitra (IEEE Micro, 2005)

Optimized reseeding by seed ordering and encoding. - Ahmad A. Al-Yamani; Subhasish Mitra; Edward J. McCluskey (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Application-independent testing of FPGA interconnects. - Mehdi Baradaran Tahoori; Subhasish Mitra (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Should Logic SER be Solved at the Circuit Level? - T. M. Mak; Subhasish Mitra (IOLTS, 2006)

Combinational Logic Soft Error Correction. - Subhasish Mitra; Ming Zhang 017; Saad Waqas; Norbert Seifert; Balkaran S. Gill; Kee Sup Kim (ITC, 2006)

Signature Analyzer Design for Yield Learning Support. - Nishant Patil; Subhasish Mitra; Steven S. Lumetta (ITC, 2006)

Test Compression for FPGAs. - Mehdi Baradaran Tahoori; Subhasish Mitra (ITC, 2006)

How To Safeguard Your Sensitive Data. - Bob Mungamuru; Hector Garcia-Molina; Subhasish Mitra (SRDS, 2006)

Soft Error Resilient System Design through Error Correction. - Subhasish Mitra; Ming Zhang 017; Norbert Seifert; T. M. Mak; Kee Sup Kim (VLSI-SoC (Selected Papers), 2006)

Evaluation of Test Metrics: Stuck-at, Bridge Coverage Estimate and Gate Exhaustive. - Ruifeng Guo; Subhasish Mitra; M. Enamul Amyeen; Jinkyu Lee; Srihari Sivaraj; Srikanth Venkataraman (VTS, 2006)

Conference Reports. - Subhasish Mitra; Ondrej Novák; Hana Kubátová; Bashir M. Al-Hashimi; Erik Jan Marinissen; C. P. Ravikumar (IEEE Des. Test Comput., 2006)

XPAND: An Efficient Test Stimulus Compression Technique. - Subhasish Mitra; Kee Sup Kim (IEEE Trans. Computers, 2006)

Sequential Element Design With Built-In Soft Error Resilience. - Ming Zhang 017; Subhasish Mitra; T. M. Mak; Norbert Seifert; Nicholas J. Wang; Quan Shi; Kee Sup Kim; Naresh R. Shanbhag; Sanjay J. Patel (IEEE Trans. Very Large Scale Integr. Syst., 2006)

Automated Design of Misaligned-Carbon-Nanotube-Immune Circuits. - Nishant Patil; Jie Deng; H.-S. Philip Wong; Subhasish Mitra (DAC, 2007)

Verification-guided soft error resilience. - Sanjit A. Seshia; Wenchao Li 001; Subhasish Mitra (DATE, 2007)

Circuit Failure Prediction Enables Robust System Design Resilient to Aging and Wearout. - Subhasish Mitra (IOLTS, 2007)

Soft Errors: Technology Trends, System Effects, and Protection Techniques. - Subhasish Mitra; Pia N. Sanda; Norbert Seifert (IOLTS, 2007)

Carbon Nanotube Transistor Circuits: Circuit-Level Performance Benchmarking and Design Options for Living with Imperfections. - Jie Deng; Nishant Patil; Koungmin Ryu; Alexander Badmaev; Chongwu Zhou; Subhasish Mitra; H.-S. Philip Wong (ISSCC, 2007)

California scan architecture for high quality and low power testing. - Kyoung Youn Cho; Subhasish Mitra; Edward J. McCluskey (ITC, 2007)

Circuit failure prediction to overcome scaled CMOS reliability challenges. - Subhasish Mitra; Mridul Agarwal (ITC, 2007)

Circuit Failure Prediction and Its Application to Transistor Aging. - Mridul Agarwal; Bipul C. Paul; Ming Zhang; Subhasish Mitra (VTS, 2007)

Application-Dependent Delay Testing of FPGAs. - Mehdi Baradaran Tahoori; Subhasish Mitra (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

IFRA: instruction footprint recording and analysis for post-silicon bug localization in processors. - Sung-Boem Park; Subhasish Mitra (DAC, 2008)

Soft Errors: System Effects, Protection Techniques and Case Studies. - Dimitris Gizopoulos; Kaushik Roy 001; Subhasish Mitra; Pia N. Sanda (DATE, 2008)

CASP: Concurrent Autonomous Chip Self-Test Using Stored Test Patterns. - Yanjing Li; Samy Makar; Subhasish Mitra (DATE, 2008)

Globally Optimized Robust Systems to Overcome Scaled CMOS Reliability Challenges. - Subhasish Mitra (DATE, 2008)

Dependable Embedded Systems Special Day Panel: Issues and Challenges in Dependable Embedded Systems. - Neeraj Suri; Christof Fetzer; Jacob A. Abraham; Stefan Poledna; Avi Mendelson; Subhasish Mitra (DATE, 2008)

Design Guidelines for Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits. - Jie Zhang 007; Nishant Patil; Subhasish Mitra (DATE, 2008)

A low-overhead fault tolerance scheme for TSV-based 3D network on chip links. - Igor Loi; Subhasish Mitra; Thomas H. Lee; Shinobu Fujita; Luca Benini (ICCAD, 2008)

Reliable system design: models, metrics and design techniques. - Subhasish Mitra; Ravishankar K. Iyer; Kishor S. Trivedi; James W. Tschanz (ICCAD, 2008)

Soft Error Protection Techniques. - Subhasish Mitra (IOLTS, 2008)

Tutorial 4: Robust System Design in Scaled CMOS. - Subhasish Mitra (ISQED, 2008)

Optimized Circuit Failure Prediction for Aging: Practicality and Promise. - Mridul Agarwal; Varsha Balakrishnan; Anshuman Bhuyan; Kyunglok Kim; Bipul C. Paul; Wenping Wang 004; Bo Yang; Yu Cao 001; Subhasish Mitra (ITC, 2008)

VAST: Virtualization-Assisted Concurrent Autonomous Self-Test. - Hiroaki Inoue; Yanjing Li; Subhasish Mitra (ITC, 2008)

Gate-Oxide Early Life Failure Prediction. - Tze Wee Chen; Kyunglok Kim; Young Moon Kim; Subhasish Mitra (VTS, 2008)

Historical Perspective on Scan Compression. - Rohit Kapur; Subhasish Mitra; Thomas W. Williams (IEEE Des. Test Comput., 2008)

The Search for Alternative Computational Paradigms. - Naresh R. Shanbhag; Subhasish Mitra; Gustavo de Veciana; Michael Orshansky; Radu Marculescu; Jaijeet S. Roychowdhury; Douglas L. Jones; Jan M. Rabaey (IEEE Des. Test Comput., 2008)

Design Methods for Misaligned and Mispositioned Carbon-Nanotube Immune Circuits. - Nishant Patil; Jie Deng; Albert Lin 002; H.-S. Philip Wong; Subhasish Mitra (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Circuit aging prediction for low-power operation. - Rui Zheng; Jyothi Velamala; Vijay Reddy; Varsha Balakrishnan; Evelyn Mintarno; Subhasish Mitra; Srikanth Krishnan; Yu Cao 001 (CICC, 2009)

Digital VLSI logic technology using Carbon Nanotube FETs: frequently asked questions. - Nishant Patil; Albert Lin 002; Jie Zhang 007; H.-S. Philip Wong; Subhasish Mitra (DAC, 2009)

Carbon nanotube circuits in the presence of carbon nanotube density variations. - Jie Zhang 007; Nishant Patil; Arash Hazeghi; Subhasish Mitra (DAC, 2009)

Imperfection-immune VLSI logic circuits using Carbon Nanotube Field Effect Transistors. - Subhasish Mitra; Jie Zhang 007; Nishant Patil; Hai Wei (DATE, 2009)

IFRA: Post-silicon bug localization in processors. - Sung-Boem Park; Subhasish Mitra (HLDVT, 2009)

Nanoelectromechanical (NEM) relays integrated with CMOS SRAM for improved stability and low leakage. - Soogine Chong; Kerem Akarvardar; Roozbeh Parsa; Jun-Bo Yoon; Roger T. Howe; Subhasish Mitra; H.-S. Philip Wong (ICCAD, 2009)

Operating system scheduling for efficient online self-test in robust systems. - Yanjing Li; Onur Mutlu; Subhasish Mitra (ICCAD, 2009)

Imperfection-immune Carbon Nanotube digital VLSI. - Nishant Patil; Subhasish Mitra (ICCD, 2009)

Testing for Transistor Aging. - A. Hakan Baba; Subhasish Mitra (VTS, 2009)

Overcoming Early-Life Failure and Aging for Robust Systems. - Yanjing Li; Young Moon Kim; Evelyn Mintarno; Donald S. Gardner; Subhasish Mitra (IEEE Des. Test Comput., 2009)

The case for RAMClouds: scalable high-performance storage entirely in DRAM. - John K. Ousterhout; Parag Agrawal; David Erickson; Christos Kozyrakis; Jacob Leverich; David Mazières; Subhasish Mitra; Aravind Narayanan; Guru M. Parulkar; Mendel Rosenblum; Stephen M. Rumble; Eric Stratmann; et al. (ACM SIGOPS Oper. Syst. Rev., 2009)

Post-Silicon Bug Localization in Processors Using Instruction Footprint Recording and Analysis (IFRA). - Sung-Boem Park; Ted Hong; Subhasish Mitra (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Probabilistic Analysis and Design of Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits. - Jie Zhang 007; Nishant Patil; Subhasish Mitra (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Post-silicon validation opportunities, challenges and recent advances. - Subhasish Mitra; Sanjit A. Seshia; Nicola Nicolici (DAC, 2010)

BLoG: post-silicon bug localization in processors using bug localization graphs. - Sung-Boem Park; Anne Bracy; Hong Wang 003; Subhasish Mitra (DAC, 2010)

Carbon nanotube correlation: promising opportunity for CNFET circuit yield enhancement. - Jie Zhang 007; Shashikanth Bobba; Nishant Patil; Albert Lin 002; H.-S. Philip Wong; Giovanni De Micheli; Subhasish Mitra (DAC, 2010)

Statistical static timing analysis using Markov chain Monte Carlo. - Yashodhan Kanoria; Subhasish Mitra; Andrea Montanari (DATE, 2010)

ERSA: Error Resilient System Architecture for probabilistic applications. - Larkhoon Leem; Hyungmin Cho; Jason Bau; Quinn A. Jacobson; Subhasish Mitra (DATE, 2010)

Optimized self-tuning for circuit aging. - Evelyn Mintarno; Joëlle Skaf; Rui Zheng; Jyothi Velamala; Yu Cao 001; Stephen P. Boyd; Robert W. Dutton; Subhasish Mitra (DATE, 2010)

Cross-layer resilience challenges: Metrics and optimization. - Subhasish Mitra; Kevin Brelsford; Pia N. Sanda (DATE, 2010)

Carbon nanotube circuits: Living with imperfections and variations. - Jie Zhang 007; Nishant Patil; Albert Lin 002; H.-S. Philip Wong; Subhasish Mitra (DATE, 2010)

Efficient FPGAs using nanoelectromechanical relays. - Chen Chen 018; Roozbeh Parsa; Nishant Patil; Soogine Chong; Kerem Akarvardar; J. Provine; David Lewis; Jeff Watt; Roger T. Howe; H.-S. Philip Wong; Subhasish Mitra (FPGA, 2010)

Cross-layer error resilience for robust systems. - Larkhoon Leem; Hyungmin Cho; Hsiao-Heng Lee; Young Moon Kim; Yanjing Li; Subhasish Mitra (ICCAD, 2010)

QED: Quick Error Detection tests for effective post-silicon validation. - Ted Hong; Yanjing Li; Sung-Boem Park; Diana Mui; David Lin; Ziyad Abdel Kaleq; Nagib Hakim; Helia Naeimi; Donald S. Gardner; Subhasish Mitra (ITC, 2010)

Robust System Design. - Subhasish Mitra (VLSI Design, 2010)

Gate-oxide early-life failure identification using delay shifts. - Young Moon Kim; Tze Wee Chen; Yoshio Kameda; Masayuki Mizuno; Subhasish Mitra (VTS, 2010)

Concurrent autonomous self-test for uncore components in system-on-chips. - Yanjing Li; Onur Mutlu; Donald S. Gardner; Subhasish Mitra (VTS, 2010)

Post-silicon bug localization for processors using IFRA. - Sung-Boem Park; Subhasish Mitra (Commun. ACM, 2010)

Carbon nanotube imperfection-immune digital VLSI: Frequently asked questions updated. - Hai Wei; Jie Zhang 007; Lan Wei; Nishant Patil; Albert Lin 002; Max M. Shulaker; Hong-Yu Chen; H.-S. Philip Wong; Subhasish Mitra (ICCAD, 2011)

Architecture and performance evaluation of 3D CMOS-NEM FPGA. - Chen Dong 003; Chen Chen 018; Subhasish Mitra; Deming Chen (SLIP, 2011)

The case for RAMCloud. - John K. Ousterhout; Parag Agrawal; David Erickson; Christos Kozyrakis; Jacob Leverich; David Mazières; Subhasish Mitra; Aravind Narayanan; Diego Ongaro; Guru M. Parulkar; Mendel Rosenblum; Stephen M. Rumble; et al. (Commun. ACM, 2011)

Robust System Design to Overcome CMOS Reliability Challenges. - Subhasish Mitra; Kevin Brelsford; Young Moon Kim; Hsiao-Heng Lee; Yanjing Li (IEEE J. Emerg. Sel. Topics Circuits Syst., 2011)

Robust System Design. - Subhasish Mitra; Hyungmin Cho; Ted Hong; Young Moon Kim; Hsiao-Heng Lee; Larkhoon Leem; Yanjing Li; David Lin; Evelyn Mintarno; Diana Mui; Sung-Boem Park; Nishant Patil; et al. (IPSJ Trans. Syst. LSI Des. Methodol., 2011)

Characterization and Implementation of Fault-Tolerant Vertical Links for 3-D Networks-on-Chip. - Igor Loi; Federico Angiolini; Shinobu Fujita; Subhasish Mitra; Luca Benini (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Self-Tuning for Maximized Lifetime Energy-Efficiency in the Presence of Circuit Aging. - Evelyn Mintarno; Joëlle Skaf; Rui Zheng; Jyothi Velamala; Yu Cao 001; Stephen P. Boyd; Robert W. Dutton; Subhasish Mitra (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Characterization and Design of Logic Circuits in the Presence of Carbon Nanotube Density Variations. - Jie Zhang 007; Nishant Patil; Arash Hazeghi; H.-S. Philip Wong; Subhasish Mitra (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Nano-Electro-Mechanical (NEM) relays and their application to FPGA routing. - Chen Chen 018; W. Scott Lee; J. Provine; Soogine Chong; Roozbeh Parsa; Daesung Lee 002; Roger T. Howe; H.-S. Philip Wong; Subhasish Mitra (ASP-DAC, 2012)

Bug localization techniques for effective post-silicon validation. - Subhasish Mitra; David Lin; Nagib Hakim; Donald S. Gardner (ASP-DAC, 2012)

Quick detection of difficult bugs for effective post-silicon validation. - David Lin; Ted Hong; Farzan Fallah; Nagib Hakim; Subhasish Mitra (DAC, 2012)

Nano-Electro-Mechanical relays for FPGA routing: Experimental demonstration and a design technique. - Chen Chen 018; W. Scott Lee; Roozbeh Parsa; Soogine Chong; J. Provine; Jeff Watt; Roger T. Howe; H.-S. Philip Wong; Subhasish Mitra (DATE, 2012)

Probabilistic analysis of Gallager B faulty decoder. - S. M. Sadegh Tabatabaei Yazdi; Hyungmin Cho; Yifan Sun 001; Subhasish Mitra; Lara Dolecek (ICC, 2012)

Tutorial T6: Variability-resistant Software and Hardware for Nano-Scale Computing. - Nikil D. Dutt; Mani B. Srivastava; Rajesh Gupta 001; Subhasish Mitra (VLSI Design, 2012)

Editorial. - Giovanni De Micheli; Subhasish Mitra; Maciej Ogorzalek (IEEE J. Emerg. Sel. Topics Circuits Syst., 2012)

ERSA: Error Resilient System Architecture for Probabilistic Applications. - Hyungmin Cho; Larkhoon Leem; Subhasish Mitra (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Carbon Nanotube Robust Digital VLSI. - Jie Zhang 007; Albert Lin 002; Nishant Patil; Hai Wei; Lan Wei; H.-S. Philip Wong; Subhasish Mitra (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Detection of early-life failures in high-K metal-gate transistors and ultra low-K inter-metal dielectrics. - Young Moon Kim; Jun Seomun; Hyung-Ock Kim; Kyung Tae Do; Jung Yun Choi; Kee Sup Kim; Matthias Sauer 002; Bernd Becker 001; Subhasish Mitra (CICC, 2013)

Quantitative evaluation of soft error injection techniques for robust system design. - Hyungmin Cho; Shahrzad Mirkhani; Chen-Yong Cher; Jacob A. Abraham; Subhasish Mitra (DAC, 2013)

Rapid exploration of processing and design guidelines to overcome carbon nanotube variations. - Gage Hills; Jie Zhang 007; Charles Mackin; Max M. Shulaker; Hai Wei; H.-S. Philip Wong; Subhasish Mitra (DAC, 2013)

Sacha: the Stanford carbon nanotube controlled handshaking robot. - Max M. Shulaker; Jelle Van Rethy; Gage Hills; Hong-Yu Chen; Georges G. E. Gielen; H.-S. Philip Wong; Subhasish Mitra (DAC, 2013)

Overcoming post-silicon validation challenges through quick error detection (QED). - David Lin; Ted Hong; Yanjing Li; Farzan Fallah; Donald S. Gardner; Nagib Hakim; Subhasish Mitra (DATE, 2013)

Carbon nanotube circuits: opportunities and challenges. - Hai Wei; Max M. Shulaker; Gage Hills; Hong-Yu Chen; Chi-Shuen Lee; Luckshitha Liyanage; Jie Zhang 007; H.-S. Philip Wong; Subhasish Mitra (DATE, 2013)

Carbon nanotube imperfection-immune digital VLSI. - Subhasish Mitra (ISLPED, 2013)

Experimental demonstration of a fully digital capacitive sensor interface built entirely using carbon-nanotube FETs. - Max M. Shulaker; Jelle Van Rethy; Gage Hills; Hong-Yu Chen; Georges G. E. Gielen; H.-S. Philip Wong; Subhasish Mitra (ISSCC, 2013)

Self-repair of uncore components in robust system-on-chips: An OpenSPARC T2 case study. - Yanjing Li; Eric Cheng; Samy Makar; Subhasish Mitra (ITC, 2013)

Early-life-failure detection using SAT-based ATPG. - Matthias Sauer 002; Young Moon Kim; Jun Seomun; Hyung-Ock Kim; Kyung Tae Do; Jung Yun Choi; Kee Sup Kim; Subhasish Mitra; Bernd Becker 001 (ITC, 2013)

Combinational Logic Design Using Six-Terminal NEM Relays. - Daesung Lee 002; W. Scott Lee; Chen Chen 018; Farzan Fallah; J. Provine; Soogine Chong; John Watkins; Roger T. Howe; H.-S. Philip Wong; Subhasish Mitra (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Underdesigned and Opportunistic Computing in Presence of Hardware Variability. - Puneet Gupta 001; Yuvraj Agarwal; Lara Dolecek; Nikil D. Dutt; Rajesh K. Gupta 001; Rakesh Kumar 002; Subhasish Mitra; Alexandru Nicolau; Tajana Simunic Rosing; Mani B. Srivastava; Steven Swanson; Dennis Sylvester (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

QED post-silicon validation and debug: Frequently asked questions. - David Lin; Subhasish Mitra (ASP-DAC, 2014)

Rethinking error injection for effective resilience. - Shahrzad Mirkhani; Hyungmin Cho; Subhasish Mitra; Jacob A. Abraham (ASP-DAC, 2014)

Robust design and experimental demonstrations of carbon nanotube digital circuits. - Gage Hills; Max M. Shulaker; Hai Wei; Hong-Yu Chen; H.-S. Philip Wong; Subhasish Mitra (CICC, 2014)

Cross layer resiliency in real world. - Vikas Chandra; Subhasish Mitra; Chen-Yong Cher; Silvia Melitta Müller (DATE, 2014)

QED post-silicon validation and debug: Invited abstract. - David Lin; Subhasish Mitra (ISIC, 2014)

Carbon nanotube computer: transforming scientific discoveries into working systems. - Subhasish Mitra (ISPD, 2014)

A new era of computing: Are you "ready now" to build a smarter and secured enterprise? - Jacqueline Woods; Sridhar Iyengar; Amit Sinha; Subhasish Mitra; Stacy Cannady (ISQED, 2014)

Welcome message. - Michael Purtell; Subhasish Mitra (ITC, 2014)

The resilience wall: Cross-layer solution strategies. - Subhasish Mitra; Pradip Bose; Eric Cheng; Chen-Yong Cher; Hyungmin Cho; Rajiv V. Joshi; Young Moon Kim; Charles R. Lefurgy; Yanjing Li; Kenneth P. Rodbell; Kevin Skadron; James H. Stathis; et al. (VLSI-DAT, 2014)

Guest Editorial: Robust and energy-secure systems. - Augusto Vega; Simha Sethumadhavan; Subhasish Mitra (IEEE J. Emerg. Sel. Topics Circuits Syst., 2014)

Addressing failures in exascale computing. - Marc Snir; Robert W. Wisniewski; Jacob A. Abraham; Sarita V. Adve; Saurabh Bagchi; Pavan Balaji; James F. Belak; Pradip Bose; Franck Cappello; Bill Carlson; Andrew A. Chien; Paul Coteus; et al. (Int. J. High Perform. Comput. Appl., 2014)

System Level Benchmarking with Yield-Enhanced Standard Cell Library for Carbon Nanotube VLSI Circuits. - Shashikanth Bobba; Jie Zhang 007; Pierre-Emmanuel Gaillardon; H.-S. Philip Wong; Subhasish Mitra; Giovanni De Micheli (ACM J. Emerg. Technol. Comput. Syst., 2014)

Sensor-to-Digital Interface Built Entirely With Carbon Nanotube FETs. - Max M. Shulaker; Jelle Van Rethy; Gage Hills; Hai Wei; Hong-Yu Chen; Georges G. E. Gielen; H.-S. Philip Wong; Subhasish Mitra (IEEE J. Solid State Circuits, 2014)

Effective Post-Silicon Validation of System-on-Chips Using Quick Error Detection. - David Lin; Ted Hong; Yanjing Li; Eswaran S; Sharad Kumar; Farzan Fallah; Nagib Hakim; Donald S. Gardner; Subhasish Mitra (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Multiple Independent Gate FETs: How many gates do we need? - Luca Gaetano Amarù; Gage Hills; Pierre-Emmanuel Gaillardon; Subhasish Mitra; Giovanni De Micheli (ASP-DAC, 2015)

Hybrid quick error detection (H-QED): accelerator validation and debug using high-level synthesis principles. - Keith A. Campbell; David Lin; Subhasish Mitra; Deming Chen (DAC, 2015)

Understanding soft errors in uncore components. - Hyungmin Cho; Chen-Yong Cher; Thomas Shepherd; Subhasish Mitra (DAC, 2015)

Quick error detection tests with fast runtimes for effective post-silicon validation and debug. - David Lin; Eswaran S; Sharad Kumar; Eric Rentschler; Subhasish Mitra (DATE, 2015)

Efficient soft error vulnerability estimation of complex designs. - Shahrzad Mirkhani; Subhasish Mitra; Chen-Yong Cher; Jacob A. Abraham (DATE, 2015)

Monolithic 3D integration: a path from concept to reality. - Max M. Shulaker; Tony F. Wu; Mohamed M. Sabry; Hai Wei; H.-S. Philip Wong; Subhasish Mitra (DATE, 2015)

Time-based sensor interface circuits in carbon nanotube technology. - Georges G. E. Gielen; Jelle Van Rethy; Max M. Shulaker; Gage Hills; H.-S. Philip Wong; Subhasish Mitra (ISCAS, 2015)

A structured approach to post-silicon validation and debug using symbolic quick error detection. - David Lin; Eshan Singh; Clark W. Barrett; Subhasish Mitra (ITC, 2015)

Energy-Efficient Abundant-Data Computing: The N3XT 1, 000x. - Mohamed M. Sabry; Mingyu Gao 001; Gage Hills; Chi-Shuen Lee; Greg Pitner; Max M. Shulaker; Tony F. Wu; Mehdi Asheghi; Jeffrey Bokor; Franz Franchetti; Kenneth E. Goodson; Christos Kozyrakis; et al. (Computer, 2015)

NSF expedition on variability-aware software: Recent results and contributions. - Lucas Francisco Wanner; Liangzhen Lai; Abbas Rahimi; Mark Gottscho; Pietro Mercati; Chu-Hsiang Huang; Frederic Sala; Yuvraj Agarwal; Lara Dolecek; Nikil D. Dutt; Puneet Gupta 001; Rajesh K. Gupta 001; et al. (it Inf. Technol., 2015)

New Logic Synthesis as Nanotechnology Enabler. - Luca Gaetano Amarù; Pierre-Emmanuel Gaillardon; Subhasish Mitra; Giovanni De Micheli (Proc. IEEE, 2015)

Rapid Co-Optimization of Processing and Circuit Design to Overcome Carbon Nanotube Variations. - Gage Hills; Jie Zhang 007; Max Marcel Shulaker; Hai Wei; Chi-Shuen Lee; Arjun Balasingam; H.-S. Philip Wong; Subhasish Mitra (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Nano-engineered architectures for ultra-low power wireless body sensor nodes. - Rubén Braojos; David Atienza; Mohamed M. Sabry Aly; Tony F. Wu; H.-S. Philip Wong; Subhasish Mitra; Giovanni Ansaloni (CODES+ISSS, 2016)

Clear: cross-layer exploration for architecting resilience combining hardware and software techniques to tolerate soft errors in processor cores. - Eric Cheng; Shahrzad Mirkhani; Lukasz G. Szafaryn; Chen-Yong Cher; Hyungmin Cho; Kevin Skadron; Mircea R. Stan; Klas Lilja; Jacob A. Abraham; Pradip Bose; Subhasish Mitra (DAC, 2016)

Cross-layer resilience. - Subhasish Mitra (ETS, 2016)

Session 24 overview: Ultra-efficient computing: Application-inspired and analog-assisted digital. - Antoine Dupret; Subhasish Mitra (ISSCC, 2016)

Transforming nanodevices into nanosystems: The N3XT 1, 000X. - Subhasish Mitra (LATS, 2016)

Transforming nanodevices to next generation nanosystems. - Max Marcel Shulaker; Gage Hills; H.-S. Philip Wong; Subhasish Mitra (SAMOS, 2016)

Symbolic Quick Error Detection for Pre-Silicon and Post-Silicon Validation: Frequently Asked Questions. - Eshan Singh; David Lin; Clark W. Barrett; Subhasish Mitra (IEEE Des. Test, 2016)

TPAD: Hardware Trojan Prevention and Detection for Trusted Integrated Circuits. - Tony F. Wu; Karthik Ganesan 001; Yunqing Alexander Hu; H.-S. Philip Wong; S. Simon Wong; Subhasish Mitra (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

Time-Based Sensor Interface Circuits in CMOS and Carbon Nanotube Technologies. - Georges G. E. Gielen; Jelle Van Rethy; Jorge Marin; Max M. Shulaker; Gage Hills; H.-S. Philip Wong; Subhasish Mitra (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

ASP-DAC 2017 keynote speech I: In memory of Edward J. McCluskey: The next wave of pioneering innovations. - Subhasish Mitra; Deming Chen (ASP-DAC, 2017)

E-QED: Electrical Bug Localization During Post-silicon Validation Enabled by Quick Error Detection and Formal Methods. - Eshan Singh; Clark W. Barrett; Subhasish Mitra (CAV (2), 2017)

3D nanosystems enable embedded abundant-data computing: special session paper. - William Hwang; Mohamed M. Sabry Aly; Yash H. Malviya; Mingyu Gao 001; Tony F. Wu; Christos Kozyrakis; H.-S. Philip Wong; Subhasish Mitra (CODES+ISSS, 2017)

A Systems Approach to Computing in Beyond CMOS Fabrics: Invited. - Ameya Patil; Naresh R. Shanbhag; Lav R. Varshney; Eric Pop; H.-S. Philip Wong; Subhasish Mitra; Jan M. Rabaey; Jeffrey A. Weldon; Larry T. Pileggi; Sasikanth Manipatruni; Dmitri E. Nikonov; Ian A. Young (DAC, 2017)

Very Low Voltage (VLV) Design. - Ramon Bertran; Pradip Bose; David M. Brooks; Jeff Burns; Alper Buyuktosunoglu; Nandhini Chandramoorthy; Eric Cheng; Martin Cochet; Schuyler Eldridge; Daniel Friedman; Hans M. Jacobson; Rajiv V. Joshi; et al. (ICCD, 2017)

Cross-Layer Resilience in Low-Voltage Digital Systems: Key Insights. - Eric Cheng; Jacob A. Abraham; Pradip Bose; Alper Buyuktosunoglu; Keith A. Campbell; Deming Chen; Chen-Yong Cher; Hyungmin Cho; Binh Q. Le; Klas Lilja; Shahrzad Mirkhani; Kevin Skadron; et al. (ICCD, 2017)

Logic Bug Detection and Localization Using Symbolic Quick Error Detection. - Eshan Singh; David Lin; Clark W. Barrett; Subhasish Mitra (CoRR, 2017)

Edward J. McCluskey 1929-2016. - Michael J. Flynn; Subhasish Mitra (IEEE Des. Test, 2017)

Introduction to the January Special Issue on the 2016 IEEE International Solid-State Circuits Conference. - Dennis Sylvester; Dejan Markovic; Roman Genov; Atsushi Kawasumi; Subhasish Mitra (IEEE J. Solid State Circuits, 2017)

Hot Chips 28. - Bryan Chin; Subhasish Mitra (IEEE Micro, 2017)

System-Level Effects of Soft Errors in Uncore Components. - Hyungmin Cho; Eric Cheng; Thomas Shepherd; Chen-Yong Cher; Subhasish Mitra (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Resistive RAM-Centric Computing: Design and Modeling Methodology. - Haitong Li; Tony F. Wu; Subhasish Mitra; H.-S. Philip Wong (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

TRIG: hardware accelerator for inference-based applications and experimental demonstration using carbon nanotube FETs. - Gage Hills; Daniel Bankman; Bert Moons; Lita Yang; Jake Hillard; Alex Kahng; Rebecca Park; Marian Verhelst; Boris Murmann; Max M. Shulaker; H.-S. Philip Wong; Subhasish Mitra (DAC, 2018)

Symbolic quick error detection using symbolic initial state for pre-silicon verification. - Mohammad Rahmani Fadiheh; Joakim Urdahl; Srinivasa Shashank Nuthakki; Subhasish Mitra; Clark W. Barrett; Dominik Stoffel; Wolfgang Kunz (DATE, 2018)

ETISS-ML: A multi-level instruction set simulator with RTL-level fault injection support for the evaluation of cross-layer resiliency techniques. - Daniel Mueller-Gritschneder; Martin Dittrich; Josef Weinzierl; Eric Cheng; Subhasish Mitra; Ulf Schlichtmann (DATE, 2018)

Coming Up N3XT, After 2D Scaling of Si CMOS. - William Hwang; Weier Wan; Subhasish Mitra; H.-S. Philip Wong (ISCAS, 2018)

Brain-inspired computing exploiting carbon nanotube FETs and resistive RAM: Hyperdimensional computing case study. - Tony F. Wu; Haitong Li; Ping-Chen Huang; Abbas Rahimi; Jan M. Rabaey; H.-S. Philip Wong; Max M. Shulaker; Subhasish Mitra (ISSCC, 2018)

Abundant-data computing: The N3XT 1, 000X. - Subhasish Mitra (VLSI-DAT, 2018)

Hyperdimensional Computing Nanosystem. - Abbas Rahimi; Tony F. Wu; Haitong Li; Jan M. Rabaey; H.-S. Philip Wong; Max M. Shulaker; Subhasish Mitra (CoRR, 2018)

Hyperdimensional Computing Exploiting Carbon Nanotube FETs, Resistive RAM, and Their Monolithic 3D Integration. - Tony F. Wu; Haitong Li; Ping-Chen Huang; Abbas Rahimi; Gage Hills; Bryce Hodson; William Hwang; Jan M. Rabaey; H.-S. Philip Wong; Max M. Shulaker; Subhasish Mitra (IEEE J. Solid State Circuits, 2018)

Tolerating Soft Errors in Processor Cores Using CLEAR (Cross-Layer Exploration for Architecting Resilience). - Eric Cheng; Shahrzad Mirkhani; Lukasz G. Szafaryn; Chen-Yong Cher; Hyungmin Cho; Kevin Skadron; Mircea R. Stan; Klas Lilja; Jacob A. Abraham; Pradip Bose; Subhasish Mitra (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Cross-Layer Resilience: Challenges, Insights, and the Road Ahead. - Eric Cheng; Daniel Mueller-Gritschneder; Jacob A. Abraham; Pradip Bose; Alper Buyuktosunoglu; Deming Chen; Hyungmin Cho; Yanjing Li; Uzair Sharif; Kevin Skadron; Mircea Stan; Ulf Schlichtmann; et al. (DAC, 2019)

Processor Hardware Security Vulnerabilities and their Detection by Unique Program Execution Checking. - Mohammad Rahmani Fadiheh; Dominik Stoffel; Clark W. Barrett; Subhasish Mitra; Wolfgang Kunz (DATE, 2019)

Review of Methodologies for Pre- and Post-Silicon Analog Verification in Mixed-Signal SOCs. - Georges G. E. Gielen; Nektar Xama; Karthik Ganesan 001; Subhasish Mitra (DATE, 2019)

Symbolic QED Pre-silicon Verification for Automotive Microcontroller Cores: Industrial Case Study. - Eshan Singh; Keerthikumara Devarajegowda; Sebastian Simon; Ralf Schnieder; Karthik Ganesan 001; Mohammad Rahmani Fadiheh; Dominik Stoffel; Wolfgang Kunz; Clark W. Barrett; Wolfgang Ecker; Subhasish Mitra (DATE, 2019)

Unlocking the Power of Formal Hardware Verification with CoSA and Symbolic QED: Invited Paper. - Florian Lonsing; Karthik Ganesan 001; Makai Mann; Srinivasa Shashank Nuthakki; Eshan Singh; Mario Srouji; Yahan Yang; Subhasish Mitra; Clark W. Barrett (ICCAD, 2019)

A 43pJ/Cycle Non-Volatile Microcontroller with 4.7μs Shutdown/Wake-up Integrating 2.3-bit/Cell Resistive RAM and Resilience Techniques. - Tony F. Wu; Binh Q. Le; Robert M. Radway; Andrew Bartolo; William Hwang; Seungbin Jeong; Haitong Li; Pulkit Tandon; Elisa Vianello; Pascal Vivet; Etienne Nowak; Mary Wootters; et al. (ISSCC, 2019)

Optimization of Electrical Stimulation for a High-Fidelity Artificial Retina. - Nishal P. Shah; Sasidhar Madugula; Lauren E. Grosberg; Gonzalo E. Mena; Pulkit Tandon; Pawel Hottowy; Alexander Sher; Alan M. Litke; Subhasish Mitra; E. J. Chichilnisky (NER, 2019)

Memory Sizing of a Scalable SRAM In-Memory Computing Tile Based Architecture. - Roman Gauchi; Maha Kooli; Pascal Vivet; Jean-Philippe Noël; Edith Beigné; Subhasish Mitra; Henri-Pierre Charles (VLSI-SoC, 2019)

Variability Expeditions: A Retrospective. - Rajesh K. Gupta 001; Subhasish Mitra; Puneet Gupta 001 (IEEE Des. Test, 2019)

Monolithic 3-D Integration. - Mindy D. Bishop; H.-S. Philip Wong; Subhasish Mitra; Max M. Shulaker (IEEE Micro, 2019)

The N3XT Approach to Energy-Efficient Abundant-Data Computing. - Mohamed M. Sabry Aly; Tony F. Wu; Andrew Bartolo; Yash H. Malviya; William Hwang; Gage Hills; Igor L. Markov; Mary Wootters; Max M. Shulaker; H.-S. Philip Wong; Subhasish Mitra (Proc. IEEE, 2019)

A Data-Compressive Wired-OR Readout for Massively Parallel Neural Recording. - Dante Gabriel Muratore; Pulkit Tandon; Mary Wootters; E. J. Chichilnisky; Subhasish Mitra; Boris Murmann (IEEE Trans. Biomed. Circuits Syst., 2019)

Hybrid Quick Error Detection: Validation and Debug of SoCs Through High-Level Synthesis. - Keith A. Campbell; David Lin; Leon He; Liwei Yang; Swathi T. Gurumani; Kyle Rupnow; Subhasish Mitra; Deming Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

DECOY: DEflection-Driven HLS-Based Computation Partitioning for Obfuscating Intellectual PropertY. - Jianqi Chen; Monir Zaman; Yiorgos Makris; R. D. Shawn Blanton; Subhasish Mitra; Benjamin Carrión Schäfer (DAC, 2020)

A Formal Approach for Detecting Vulnerabilities to Transient Execution Attacks in Out-of-Order Processors. - Mohammad Rahmani Fadiheh; Johannes Müller 006; Raik Brinkmann; Subhasish Mitra; Dominik Stoffel; Wolfgang Kunz (DAC, 2020)

A-QED Verification of Hardware Accelerators. - Eshan Singh; Florian Lonsing; Saranyu Chattopadhyay; Maxwell Strange; Peng Wei 004; Xiaofan Zhang 001; Yuan Zhou; Deming Chen; Jason Cong; Priyanka Raina; Zhiru Zhang; Clark W. Barrett; et al. (DAC, 2020)

Gap-free Processor Verification by S2QED and Property Generation. - Keerthikumara Devarajegowda; Mohammad Rahmani Fadiheh; Eshan Singh; Clark W. Barrett; Subhasish Mitra; Wolfgang Ecker; Dominik Stoffel; Wolfgang Kunz (DATE, 2020)

A Theoretical Framework for Symbolic Quick Error Detection. - Florian Lonsing; Subhasish Mitra; Clark W. Barrett (FMCAD, 2020)

Sensory Particles with Optical Telemetry. - Karthik Ganesan 001; Thomas A. Flores; Binh Q. Le; Dante G. Muratore; Neal A. Patel; Subhasish Mitra; Boris Murmann; Daniel Palanker (ISCAS, 2020)

Reconfigurable tiles of computing-in-memory SRAM architecture for scalable vectorization. - Roman Gauchi; Valentin Egloff; Maha Kooli; Jean-Philippe Noël; Bastien Giraud; Pascal Vivet; Subhasish Mitra; Henri-Pierre Charles (ISLPED, 2020)

Message from the Technical Program Co-Chairs. - David Atienza; Subhasish Mitra; Manan Suri (VLSID, 2020)

A Density Metric for Semiconductor Technology [Point of View]. - H.-S. Philip Wong; Kerem Akarvardar; Dimitri A. Antoniadis; Jeffrey Bokor; Chenming Hu; Tsu-Jae King Liu; Subhasish Mitra; James D. Plummer; Sayeef S. Salahuddin (Proc. IEEE, 2020)

Scanning the Issue. - H.-S. Philip Wong; Kerem Akarvardar; Dimitri A. Antoniadis; Jeffrey Bokor; Chenming Hu; Tsu-Jae King Liu; Subhasish Mitra; James D. Plummer; Sayeef S. Salahuddin; Lei Deng 003; Xin-Guo Li; Song Han 003; et al. (Proc. IEEE, 2020)

Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition. - Saranyu Chattopadhyay; Florian Lonsing; Luca Piccolboni; Deepraj Soni; Peng Wei 004; Xiaofan Zhang 001; Yuan Zhou; Luca P. Carloni; Deming Chen; Jason Cong; Ramesh Karri; Zhiru Zhang; et al. (FMCAD, 2021)

Effective Pre-Silicon Verification of Processor Cores by Breaking the Bounds of Symbolic Quick Error Detection. - Karthik Ganesan 001; Florian Lonsing; Srinivasa Shashank Nuthakki; Eshan Singh; Mohammad Rahmani Fadiheh; Wolfgang Kunz; Dominik Stoffel; Clark W. Barrett; Subhasish Mitra (CoRR, 2021)

Split-Chip Design to Prevent IP Reverse Engineering. - Samuel Pagliarini; Joseph Sweeney; Ken Mai; R. D. Shawn Blanton; Larry T. Pileggi; Subhasish Mitra (IEEE Des. Test, 2021)

PEPR: Pseudo-Exhaustive Physically-Aware Region Testing. - Wei Li; Chris Nigh; Danielle Duvalsaint; Subhasish Mitra; Ronald D. Blanton (ITC, 2022)

Innovating at Speed and at Scale: A Next Generation Infrastructure for Accelerating Semiconductor Technologies. - Richard A. Gottscho; Edlyn V. Levine; Tsu-Jae King Liu; Paul C. McIntyre; Subhasish Mitra; Boris Murmann; Jan M. Rabaey; Sayeef S. Salahuddin; Willy C. Shih; H.-S. Philip Wong (CoRR, 2022)

CHIMERA: A 0.92-TOPS, 2.2-TOPS/W Edge AI Accelerator With 2-MByte On-Chip Foundry Resistive RAM for Efficient Training and Inference. - Kartik Prabhu; Albert Gural; Zainab F. Khan; Robert M. Radway; Massimo Giordano; Kalhan Koul; Rohan Doshi; John W. Kustin; Timothy Liu; Gregorio B. Lopes; Victor Turbiner; Win-San Khwa; et al. (IEEE J. Solid State Circuits, 2022)

Three-Dimensional Stacked Neural Network Accelerator Architectures for AR/VR Applications. - Lita Yang; Robert M. Radway; Yu-Hsin Chen; Tony F. Wu; Huichu Liu; Elnaz Ansari; Vikas Chandra; Subhasish Mitra; Edith Beigné (IEEE Micro, 2022)

G-QED: Generalized QED Pre-silicon Verification beyond Non-Interfering Hardware Accelerators. - Saranyu Chattopadhyay; Keerthikumara Devarajegowda; Bihan Zhao; Florian Lonsing; Brandon A. D'Agostino; Ioanna Vavelidou; Vijay Deep Bhatt; Sebastian Prebeck; Wolfgang Ecker; Caroline Trippel; Clark W. Barrett; Subhasish Mitra (DAC, 2023)

Thermal Scaffolding for Ultra-Dense 3D Integrated Circuits. - Dennis Rich; Anna Kasperovich; Mohamadali Malakoutian; Robert M. Radway; Shiho Hagiwara; Takahide Yoshikawa; Srabanti Chowdhury; Subhasish Mitra (DAC, 2023)

Ultra-Dense 3D Physical Design Unlocks New Architectural Design Points with Large Benefits. - Tathagata Srimani; Robert M. Radway; Jinwoo Kim; Kartik Prabhu; Dennis Rich; Carlo Gilardi; Priyanka Raina; Max M. Shulaker; Sung Kyu Lim; Subhasish Mitra (DATE, 2023)

EMBER: A 100 MHz, 0.86 mm2, Multiple-Bits-per-Cell RRAM Macro in 40 nm CMOS with Compact Peripherals and 1.0 pJ/bit Read Circuitry. - Luke R. Upton; Akash Levy; Michael D. Scott 002; Dennis Rich; Win-San Khwa; Yu-Der Chih; Meng-Fan Chang; Subhasish Mitra; Priyanka Raina; Boris Murmann (ESSCIRC, 2023)

PBA: Percentile-Based Level Allocation for Multiple-Bits-Per-Cell RRAM. - Anjiang Wei; Akash Levy; Pu Yi 001; Robert M. Radway; Priyanka Raina; Subhasish Mitra; Sara Achour (ICCAD, 2023)

Dendrite-inspired Computing to Improve Resilience of Neural Networks to Faults in Emerging Memory Technologies. - Lizy K. John; Felipe M. G. França; Subhasish Mitra; Zachary Susskind; Priscila M. V. Lima; Igor D. S. Miranda; Eugene B. John; Diego L. C. Dutra; Maurício Breternitz (ICRC, 2023)

Testbench on a Chip: A Yield Test Vehicle for Resistive Memory Devices. - Luke R. Upton; Guénolé Lallement; Michael D. Scott 002; Joyce Taylor; Robert M. Radway; Dennis Rich; Mark Nelson; Subhasish Mitra; Boris Murmann (ISQED, 2023)

MC-ELMM: Multi-Chip Endurance-Limited Memory Management. - Andrew M. Bartolo; Mohamed M. Sabry Aly; George Michelogiannakis; Subhasish Mitra (MEMSYS, 2023)

Partitioned Temporal Dithering for Efficient Epiretinal Electrical Stimulation. - Amrith Lotlikar; Nishal P. Shah; Alex R. Gogliettino; Ramandeep Vilkhu; Sasidhar Madugula; Lauren E. Grosberg; Pawel Hottowy; Alexander Sher; Alan M. Litke; E. J. Chichilnisky; Subhasish Mitra (NER, 2023)

Efficient Modeling and Calibration of Multi-Electrode Stimuli for Epiretinal Implants. - Praful K. Vasireddy; Alex R. Gogliettino; Jeff B. Brown; Ramandeep S. Vilkhu; Sasidhar Madugula; A. J. Phillips; Subhasish Mitra; Pawel Hottowy; Alexander Sher; Alan M. Litke; Nishal P. Shah; E. J. Chichilnisky (NER, 2023)

Building high performance transistors on carbon nanotube channel. - Gregory Pitner; Nathaniel Safron; Tzu-Ang Chao; Shengman Li; Sheng-Kai Su; Gilad Zeevi; Qing Lin; Hsin-Yuan Chiu; Matthias Passlack; Zichen Zhang 019; D. Mahaveer Sathaiya; Aslan Wei; et al. (VLSI Technology and Circuits, 2023)

Foundry Monolithic 3D BEOL Transistor + Memory Stack: Iso-performance and Iso-footprint BEOL Carbon Nanotube FET+RRAM vs. FEOL Silicon FET+RRAM. - Tathagata Srimani; Andrew C. Yu; Robert M. Radway; Dennis Rich; Mark Nelson; Simon S. Wong; Denis Murphy; Samuel Fuller; Gage Hills; Subhasish Mitra; Max M. Shulaker (VLSI Technology and Circuits, 2023)

An Exhaustive Approach to Detecting Transient Execution Side Channels in RTL Designs of Processors. - Mohammad Rahmani Fadiheh; Alex Wezel; Johannes Müller 006; Jörg Bormann; Sayak Ray; Jason M. Fung; Subhasish Mitra; Dominik Stoffel; Wolfgang Kunz (IEEE Trans. Computers, 2023)

Micro/Nano Circuits and Systems Design and Design Automation: Challenges and Opportunities. - Gert Cauwenberghs; Jason Cong; X. Sharon Hu; Siddharth Joshi 001; Subhasish Mitra; Wolfgang Porod; H.-S. Philip Wong (Proc. IEEE, 2023)

Silent Data Corruption: Test or Reliability Problem? - Erik Jan Marinissen; Harish Dattatraya Dixit; Ronald Shawn Blanton; Aaron Kuo; Wei Li; Subhasish Mitra; Chris Nigh; Ruben Purdy; Ben Kaczer; Dishant Sangani; Pieter Weckx; Philippe J. Roussel; et al. (ETS, 2024)

Faulty Function Extraction for Defective Circuits. - Chris Nigh; Ruben Purdy; Wei Li; Subhasish Mitra; R. D. Shawn Blanton (ETS, 2024)

Efficient Ultra-Dense 3D IC Power Delivery and Cooling Using 3D Thermal Scaffolding. - Dennis Rich; Tathagata Srimani; Mohamadali Malakoutian; Srabanti Chowdhury; Subhasish Mitra (ICCAD, 2024)

MINOTAUR: An Edge Transformer Inference and Training Accelerator with 12 MBytes On-Chip Resistive RAM and Fine-Grained Spatiotemporal Power Gating. - Kartik Prabhu; Robert M. Radway; Y. Jeffrey; Kai Bartolone; Massimo Giordano; Fabian Peddinghaus; Yonatan Urman; Win-San Khwa; Yu-Der Chih; Meng-Fan Chang; Subhasish Mitra; Priyanka Raina (VLSI Technology and Circuits, 2024)

High Performance Transistor of Aligned Carbon Nanotubes in a Nanosheet Structure. - Nathaniel Safron; Tzu-Ang Chao; Shengman Li; Shreyam Natani; San Lin Liew; Carlo Gilardi; Hsin-Yuan Chiu; Sheng-Kai Su; Andrew Bechdolt; Gilad Zeevi; Zichen Zhang 019; Matthias Passlack; et al. (VLSI Technology and Circuits, 2024)

Next-generation Probabilistic Computing Hardware with 3D MOSAICs, Illusion Scale-up, and Co-design. - Tathagata Srimani; Robert M. Radway; Masoud Mohseni; Kerem Yunus Çamsari; Subhasish Mitra (CoRR, 2024)

Omni 3D: BEOL-Compatible 3D Logic with Omnipresent Power, Signal, and Clock. - Suhyeong Choi; Carlo Gilardi; Paul Gutwin; Robert M. Radway; Tathagata Srimani; Subhasish Mitra (CoRR, 2024)

EMBER: Efficient Multiple-Bits-Per-Cell Embedded RRAM Macro for High-Density Digital Storage. - Akash Levy; Luke R. Upton; Michael D. Scott 002; Dennis Rich; Win-San Khwa; Yu-Der Chih; Meng-Fan Chang; Subhasish Mitra; Boris Murmann; Priyanka Raina (IEEE J. Solid State Circuits, 2024)

VLSI Test and Trust Roundtable. - Ramesh Karri; Janusz Rajski; Rob Aitken; Subhasish Mitra; Mark Tehranipoor (IEEE Des. Test, 2024)

Future Design Direction for SRAM Data Array: Hierarchical Subarray With Active Interconnect. - Hsiao-Hsuan Liu; Carlo Gilardi; Shairfe Muhammad Salahuddin; Zhenlin Pei; Pieter Schuddinck; Yang Xiang; Pieter Weckx; Geert Hellings; Marie Garcia Bardon; Julien Ryckaert; Chenyun Pan; Subhasish Mitra; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

MINOTAUR: A Posit-Based 0.42-0.50-TOPS/W Edge Transformer Inference and Training Accelerator. - Kartik Prabhu; Robert M. Radway; Jeffrey Yu; Kai Bartolone; Massimo Giordano; Fabian Peddinghaus; Yonatan Urman; Win-San Khwa; Yu-Der Chih; Meng-Fan Chang; Subhasish Mitra; Priyanka Raina (IEEE J. Solid State Circuits, 2025)

CLEAR Cross-Layer Resilience: A Retrospective. - Eric Cheng; Hyungmin Cho; Shahrzad Mirkhani; Lukasz G. Szafaryn; Jacob A. Abraham; Pradip Bose; Chen-Yong Cher; Klas Lilja; Kevin Skadron; Mircea Stan; Subhasish Mitra (IEEE Des. Test, 2025)

Silent Data Corruption by 10x Test Escapes Threatens Reliable Computing. - Subhasish Mitra; Subho Banerjee; Martin Dixon; Rama Govindaraju; Peter H. Hochschild; Eric X. Liu; Bharath Parthasarathy; Parthasarathy Ranganathan (CoRR, 2025)