A Partitioning Based Physical Scan Chain Allocation Algorithm that Minimizes Voltage Domain Crossings. - Nilabha Dev; Sandeep Bhatia; Subhasish Mukherjee; Sue Genova; Vinayak Kadam (VLSI Design, 2008)

Automation of 3D-DfT Insertion. - Sergej Deutsch; Vivek Chickermane; Brion L. Keller; Subhasish Mukherjee; Mario Konijnenburg; Erik Jan Marinissen; Sandeep Kumar Goel (Asian Test Symposium, 2011)

DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks. - Sergej Deutsch; Brion L. Keller; Vivek Chickermane; Subhasish Mukherjee; Navdeep Sood; Sandeep Kumar Goel; Ji-Jan Chen; Ashok Mehta; Frank Lee 004; Erik Jan Marinissen (ITC, 2012)

SmartScan - Hierarchical test compression for pin-limited low power designs. - Krishna Chakravadhanula; Vivek Chickermane; Don Pearl; Akhil Garg 001; R. Khurana; Subhasish Mukherjee; P. Nagaraj (ITC, 2013)

Test and debug strategy for TSMC CoWoS™ stacking process based heterogeneous 3D IC: A silicon case study. - Sandeep Kumar Goel; Saman Adham; Min-Jer Wang; Ji-Jan Chen; Tze-Chiang Huang; Ashok Mehta; Frank Lee 004; Vivek Chickermane; Brion L. Keller; Thomas Valind; Subhasish Mukherjee; Navdeep Sood; et al. (ITC, 2013)