Large Scale VLSI Circuit Simulation Using Point Relaxation. - Subhendu Roy; Yogesh Dilip Save; H. Narayanan; Sachin B. Patkar (CSC, 2010)

Reliability Aware Gate Sizing Combating NBTI and Oxide Breakdown. - Subhendu Roy; David Z. Pan (VLSID, 2014)

Triple Patterning Lithography (TPL) Layout Decomposition using End-Cutting (JM3 Special Session). - Bei Yu 001; Subhendu Roy; Jhih-Rong Gao; David Z. Pan (CoRR, 2014)

Towards Optimal Performance-Area Trade-Off in Adders by Synthesis of Parallel Prefix Structures. - Subhendu Roy; Mihir R. Choudhury; Ruchir Puri; David Z. Pan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

OSFA: a new paradigm of gate-sizing for power/performance optimizations under multiple operating conditions. - Subhendu Roy; Derong Liu 002; Junhyung Um; David Z. Pan (DAC, 2015)

Skew Bounded Buffer Tree Resynthesis For Clock Power Optimization. - Subhendu Roy; David Z. Pan; Pavlos M. Mattheakis; Peter S. Colyer; Laurent Masse-Navette; Pierre-Olivier Ribet (ACM Great Lakes Symposium on VLSI, 2015)

CSL: Coordinated and scalable logic synthesis techniques for effective NBTI reduction. - Chen-Hsuan Lin 001; Subhendu Roy; Chun-Yao Wang; David Z. Pan; Deming Chen (ICCD, 2015)

Clock Tree Resynthesis for Multi-Corner Multi-Mode Timing Closure. - Subhendu Roy; Pavlos M. Mattheakis; Laurent Masse-Navette; David Z. Pan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

LRR-DPUF: learning resilient and reliable digital physical unclonable function. - Jin Miao; Meng Li 004; Subhendu Roy; Bei Yu 001 (ICCAD, 2016)

Design for manufacturability and reliability in extreme-scaling VLSI. - Bei Yu 001; Xiaoqing Xu; Subhendu Roy; Yibo Lin; Jiaojiao Ou; David Z. Pan (Sci. China Inf. Sci., 2016)

Polynomial Time Algorithm for Area and Power Efficient Adder Synthesis in High-Performance Designs. - Subhendu Roy; Mihir R. Choudhury; Ruchir Puri; David Z. Pan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

OSFA: A New Paradigm of Aging Aware Gate-Sizing for Power/Performance Optimizations Under Multiple Operating Conditions. - Subhendu Roy; Derong Liu 002; Jagmohan Singh; Junhyung Um; David Z. Pan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

A learning bridge from architectural synthesis to physical design for exploring power efficient high-performance adders. - Subhendu Roy; Yuzhe Ma; Jin Miao; Bei Yu 001 (ISLPED, 2017)

SD-PUF: Spliced Digital Physical Unclonable Function. - Jin Miao; Meng Li 004; Subhendu Roy; Yuzhe Ma; Bei Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Cross-Layer Optimization for High Speed Adders: A Pareto Driven Machine Learning Approach. - Yuzhe Ma; Subhendu Roy; Jin Miao; Jiamin Chen; Bei Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Machine Learning for Statistical Modeling: The Case of Perpendicular Spin-Transfer-Torque Random Access Memory. - Urmimala Roy; Tanmoy Pramanik; Subhendu Roy; Avhishek Chatterjee; Leonard F. Register; Sanjay Kumar Banerjee (ACM Trans. Design Autom. Electr. Syst., 2021)

High-Speed Adder Design Space Exploration via Graph Neural Processes. - Hao Geng; Yuzhe Ma; Qi Xu; Jin Miao; Subhendu Roy; Bei Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

SMART-GPO: Gate-Level Sensitivity Measurement with Accurate Estimation for Glitch Power Optimization. - Yikang Ouyang; Yuchao Wu; Dongsheng Zuo; Subhendu Roy; Tinghuan Chen; Zhiyao Xie; Yuzhe Ma (ASP-DAC, 2025)