Design and Analysis of a Robust, High Speed, Energy Efficient 18 Transistor 1-bit Full Adder Cell, Modified with the Concept of MVT Scheme. - Subhramita Basak; Dipankar Saha; Sagar Mukherjee; Sayan Chatterjee; Chandan Kumar Sarkar (ISED, 2012)

Implementation of the Cluster Based Tunable Sleep Transistor Cell Power Gating Technique for a 4x4 Multiplier Circuit. - Dipankar Saha; Subhramita Basak; Sagar Mukherjee; Sayan Chatterjee; Chandan Kumar Sarkar (CoRR, 2013)

A Low-Voltage, Low-Power 4-bit BCD Adder, designed using the Clock Gated Power Gating, and the DVT Scheme. - Dipankar Saha; Subhramita Basak; Sagar Mukherjee; Chandan Kumar Sarkar (CoRR, 2013)