Using Hard Macros to Reduce FPGA Compilation Time. - Christopher Lavin; Marc Padilla; Subhrashankha Ghosh; Brent E. Nelson; Brad L. Hutchings; Michael J. Wirthlin (FPL, 2010)

XDL-Based Module Generators for Rapid FPGA Design Implementation. - Subhrashankha Ghosh; Brent E. Nelson (FPL, 2011)