A low cost, constant throughput and reusable 8#x00D7;8 DCT architecture for HEVC. - Subiman Chatterjee; Kishor Prabhakar Sarawadekar (MWSCAS, 2016)

Constant throughput HEVC core transform design. - Subiman Chatterjee; Kishor Sarawadekar (MWSCAS, 2016)

An Optimized Architecture of HEVC Core Transform Using Real-Valued DCT Coefficients. - Subiman Chatterjee; Kishor Sarawadekar (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

WHT and Matrix Decomposition-Based Approximated IDCT Architecture for HEVC. - Subiman Chatterjee; Kishor Sarawadekar (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

Approximated Core Transform Architectures for HEVC Using WHT-Based Decomposition Method. - Subiman Chatterjee; Kishor Sarawadekar (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Exploiting Trigonometric Properties to Optimize Higher Order DCT Architecture in HEVC. - Subiman Chatterjee; Kishor Sarawadekar (IEEE Trans. Circuits Syst. Video Technol., 2020)

Scalable Matrix Decomposition-Based Less-Complex HEVC Transform Architecture. - Subiman Chatterjee; Dinesh Bhardwaj; Binod Prasad; Kishor Sarawadekar (IEEE Trans. Consumer Electron., 2024)