Power Macromodeling for High Level Power Estimation. - Subodh Gupta; Farid N. Najm (DAC, 1997)

Power macro-models for DSP blocks with application to high-level synthesis. - Subodh Gupta; Farid N. Najm (ISLPED, 1999)

Energy-per-cycle estimation at RTL. - Subodh Gupta; Farid N. Najm (ISLPED, 1999)

Analytical models for RTL power estimation of combinational andsequential circuits. - Subodh Gupta; Farid N. Najm (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

Power modeling for high-level power estimation. - Subodh Gupta; Farid N. Najm (IEEE Trans. Very Large Scale Integr. Syst., 2000)

Bottom-Up High-Level Power Modeling and Estimation - Subodh Gupta (2000)

Energy and peak-current per-cycle estimation at RTL. - Subodh Gupta; Farid N. Najm (IEEE Trans. Very Large Scale Integr. Syst., 2003)

CAD Techniques for Power Optimization in Virtex-5 FPGAs. - Subodh Gupta; Jason Helge Anderson; Linda Farragher; Qiang Wang (CICC, 2007)

Clock power reduction for virtex-5 FPGAs. - Qiang Wang; Subodh Gupta; Jason Helge Anderson (FPGA, 2009)