Design of 1.5 GHz Quasilumped Microstrip Highpass Filter. - Deepak Sharma; Subodh Kumar Singhal; Ram Mehar Singh Dhariwal (CICSyN, 2009)

Design of 1.3 GHz Microstrip Highpass Filter Using Optimum Distributed Short Circuited Stubs. - Subodh Kumar Singhal; Deepak Sharma; Ram Mehar Singh Dhariwal (CICSyN, 2009)

Efficient architectures for VLSI implementation of 2-D discrete Hadamard transform. - Basant K. Mohanty; Pramod Kumar Meher; Subodh Kumar Singhal (ISCAS, 2012)

Area-Delay and Energy-Efficient Throughput-Scalable VLSI Architecture for SDR Channelizer. - Basant Kumar Mohanty; Subodh Kumar Singhal (Circuits Syst. Signal Process., 2016)

A high-performance VLSI architecture for reconfigurable FIR using distributed arithmetic. - Basant Kumar Mohanty; Pramod Kumar Meher; Subodh Kumar Singhal; M. N. S. Swamy (Integr., 2016)

Efficient Parallel Architecture for Fixed-Coefficient and Variable-Coefficient FIR Filters Using Distributed Arithmetic. - Subodh Kumar Singhal; Basant Kumar Mohanty (J. Circuits Syst. Comput., 2016)

Area-delay and energy efficient multi-operand binary tree adder. - Sujit Kumar Patel; Subodh Kumar Singhal (IET Circuits Devices Syst., 2020)

Efficient Diminished-1 Modulo (2n+1) Adder Using Parallel Prefix Adder. - Subodh Kumar Singhal; Basant K. Mohanty; Sujit Kumar Patel; Gaurav Saxena (J. Circuits Syst. Comput., 2020)

Area-delay efficient Radix-4 8×8 Booth multiplier for DSP applications. - Subodh Kumar Singhal; Sujit Kumar Patel; Anurag Mahajan; Gaurav Saxena (Turkish J. Electr. Eng. Comput. Sci., 2021)

An area-delay efficient single-precision floating-point multiplier for VLSI systems. - Anuradha; Sujit Kumar Patel; Subodh Kumar Singhal (Microprocess. Microsystems, 2023)