Novel Verification Framework Combining Structural and OBDD Methods in a Synthesis Environment. - Subodh M. Reddy; Wolfgang Kunz; Dhiraj K. Pradhan (DAC, 1995)

Sensitivity-Based Modeling and Methodology for Full-Chip Substrate Noise Analysis. - Rajeev Murgai; Subodh M. Reddy; Takashi Miyoshi; Takeshi Horie; Mehdi Baradaran Tahoori (DATE, 2004)

A sliding window scheme for accurate clock mesh analysis. - Hongyu Chen; Chao-Yang Yeh; Gustavo R. Wilke; Subodh M. Reddy; Hoa-van Nguyen; William W. Walker; Rajeev Murgai (ICCAD, 2005)

Analyzing timing uncertainty in mesh-based clock architectures. - Subodh M. Reddy; Gustavo R. Wilke; Rajeev Murgai (DATE, 2006)

Clock Distribution Architectures: A Comparative Study. - Chao-Yang Yeh; Gustavo R. Wilke; Hongyu Chen; Subodh M. Reddy; Hoa-van Nguyen; Takashi Miyoshi; William W. Walker; Rajeev Murgai (ISQED, 2006)

Accurate Substrate Noise Analysis Based on Library Module Characterization. - Subodh M. Reddy; Rajeev Murgai (VLSI Design, 2006)

A 3 Watt 39.8-44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS. - Nikola Nedovic; Anders Kristensson; Samir Parikh; Subodh M. Reddy; Scott McLeod; Nestoras Tzartzanis; Kouichi Kanda; Takuji Yamamoto; Satoshi Matsubara; Masaya Kibune; Yoshiyasu Doi; Satoshi Ide; et al. (IEEE J. Solid State Circuits, 2010)

A 4-channel 10.3Gb/s transceiver with adaptive phase equalizer for 4-to-41dB loss PCB channel. - Yasuo Hidaka; Takeshi Horie; Yoichi Koyanagi; Takashi Miyoshi; Hideki Osone; Samir Parikh; Subodh M. Reddy; Toshiyuki Shibuya; Yasushi Umezawa; William W. Walker (ISSCC, 2011)