Design of A Novel Highly EMI-Immune CMOS Miller OpAmp Considering Channel Length Modulation. - Subrahmanyam Boyapati; Jean-Michel Redoute; Maryam Shojaei Baghini (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

Modeling and Design of Highly EMI Immune CMOS OpAmp Topologies. - Subrahmanyam Boyapati (EMC Compo, 2024)

A 1.2 V Double-Tail StrongARM Latch Comparator with 51 fJ/comparison and 380 μV Input Noise in 65 nm CMOS Technology. - Srinivasa Rao Maram; Subrahmanyam Boyapati; Vijay Shankar Pasupureddi (ISQED, 2024)

A 7-bit 1.75-GS/s 6.9-fJ/conv.-step FoMw Loop-Unrolled Fully Asynchronous SAR ADC in 3-nm CMOS for a 224-Gb/s SerDes Receiver. - Chakravarti Bheemisetti; Karunanidhan Pandey; Idan Lotan; Gadi Ori; Ahmad Khairi; Yoel Krupnik; Udi Virobnik; Subrahmanyam Boyapati; Ariel Cohen 001; Nagendra Krishnapura (IEEE J. Solid State Circuits, 2025)