Handling irregular ILP within conventional VLIW schedulers using artificial resource constraints. - Subramanian Rajagopalan; Manish Vachharajani; Sharad Malik (CASES, 2000)

Optimal Live Range Merge for Address Register Allocation in Embedded Programs. - Guilherme Ottoni; Sandro Rigo; Guido Araujo; Subramanian Rajagopalan; Sharad Malik (CC, 2001)

A retargetable VLIW compiler framework for DSPs withinstruction-level parallelism. - Subramanian Rajagopalan; Sreeranga P. Rajan; Sharad Malik; Sandro Rigo; Guido Araujo; Koichiro Takayama (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

Retargetable Very Long Instuction Word Compiler Framework for Digital Signal Processors. - Subramanian Rajagopalan; Sharad Malik (The Compiler Design Handbook, 2002)

Design Tools for Application Specific Embedded Processors. - Wei Qin; Subramanian Rajagopalan; Manish Vachharajani; Hangsheng Wang; Xinping Zhu; David I. August; Kurt Keutzer; Sharad Malik; Li-Shiuan Peh (EMSOFT, 2002)

A formal concurrency model based architecture description language for synthesis of software development tools. - Wei Qin; Subramanian Rajagopalan; Sharad Malik (LCTES, 2004)

A Retargetable Very Long Instruction Word Compiler Framework for Digital Signal Processors. - Subramanian Rajagopalan; Sharad Malik (The Compiler Design Handbook, 2nd ed., 2007)

A 3-dimensional FEM Based Resistance Extraction. - Subramanian Rajagopalan; Shabbir H. Batterywala (VLSI Design, 2007)

Impact of Modern Process Technologies on the Electrical Parameters of Interconnects. - Debjit Sinha; Jianfeng Luo 001; Subramanian Rajagopalan; Shabbir H. Batterywala; Narendra V. Shenoy; Hai Zhou 001 (VLSI Design, 2007)

Cell Swapping Based Migration Methodology for Analog and Custom Layouts. - Shabbir H. Batterywala; Sambuddha Bhattacharya; Subramanian Rajagopalan; Hi-Keung Tony Ma; Narendra V. Shenoy (ISQED, 2008)

On Efficient and Robust Constraint Generation for Practical Layout Legalization. - Sambuddha Bhattacharya; Shabbir H. Batterywala; Subramanian Rajagopalan; Hi-Keung Tony Ma; Narendra V. Shenoy (ISQED, 2008)

Efficient Analog/RF Layout Closure with Compaction Based Legalization. - Subramanian Rajagopalan; Sambuddha Bhattacharya; Shabbir H. Batterywala (VLSI Design, 2009)

Automatic design rule correction in presence of multiple grids and track patterns. - Nitin Salodkar; Subramanian Rajagopalan; Sambuddha Bhattacharya; Shabbir H. Batterywala (DAC, 2013)

Fixing Double Patterning violations with look-ahead. - Sambuddha Bhattacharya; Subramanian Rajagopalan; Shabbir H. Batterywala (ASP-DAC, 2014)

2SAT Based Infeasibility Resolution during Design Rule Correction on Layouts with Multiple Grids. - Nitin Salodkar; Subramanian Rajagopalan; Sambuddha Bhattacharya; Shabbir H. Batterywala (VLSID, 2015)