Energy-Efficient Convolution Architecture Based on Rescheduled Dataflow. - Jihyuck Jo; Suchang Kim; In-Cheol Park (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

Hybrid Convolution Architecture for Energy-Efficient Deep Neural Network Processing. - Suchang Kim; Jihyuck Jo; In-Cheol Park (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

Real-Time SSDLite Object Detection on FPGA. - Suchang Kim; Seungho Na; Byeong Yong Kong; Jaewoong Choi; In-Cheol Park (IEEE Trans. Very Large Scale Integr. Syst., 2021)

High-Speed Counter With Novel LFSR State Extension. - Hyungjoon Bae 001; Yujin Hyun; Suchang Kim; Sangsoo Park; Jaeyoung Lee 004; Boseon Jang; Suyoung Choi; In-Cheol Park (IEEE Trans. Computers, 2023)

A CNN Inference Accelerator on FPGA With Compression and Layer-Chaining Techniques for Style Transfer Applications. - Suchang Kim; Boseon Jang; Jaeyoung Lee 004; Hyungjoon Bae 001; Hyejung Jang; In-Cheol Park (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)