Design of high-rate irregular non-binary LDPC codes using algorithmic stopping-set cancellation. - Sudarsan Vasista Srinivasan Ranganathan; Dariush Divsalar; Kasra Vakilinia; Richard D. Wesel (ISIT, 2014)

Short-blocklength non-binary LDPC codes with feedback-dependent incremental transmissions. - Kasra Vakilinia; Tsung-Yi Chen; Sudarsan Vasista Srinivasan Ranganathan; Adam R. Williamson; Dariush Divsalar; Richard D. Wesel (ISIT, 2014)

Feedback systems using non-binary LDPC codes with a limited number of transmissions. - Kasra Vakilinia; Adam R. Williamson; Sudarsan Vasista Srinivasan Ranganathan; Dariush Divsalar; Richard D. Wesel (ITW, 2014)

On the girth of (3, L) quasi-cyclic LDPC codes based on complete protographs. - Sudarsan V. S. Ranganathan; Dariush Divsalar; Richard D. Wesel (ISIT, 2015)

Universal rate-compatible LDPC code families for any increment ordering. - Sudarsan V. S. Ranganathan; Kasra Vakilinia; Dariush Divsalar; Richard D. Wesel (ISTC, 2016)

Some results on spatially coupled protograph LDPC codes. - Sudarsan V. S. Ranganathan; Kasra Vakilinia; Lara Dolecek; Dariush Divsalar; Richard D. Wesel (ITA, 2016)

Optimality and Rate-Compatibility for Erasure-Coded Packet Transmissions when Fading Channel Diversity Increases with Packet Length. - Sudarsan V. S. Ranganathan; Tong Mu; Richard D. Wesel (CoRR, 2016)

Optimizing Transmission Lengths for Limited Feedback with Non-Binary LDPC Examples. - Kasra Vakilinia; Sudarsan V. S. Ranganathan; Dariush Divsalar; Richard D. Wesel (CoRR, 2016)

Optimizing Transmission Lengths for Limited Feedback With Nonbinary LDPC Examples. - Kasra Vakilinia; Sudarsan V. S. Ranganathan; Dariush Divsalar; Richard D. Wesel (IEEE Trans. Commun., 2016)

Design of improved quasi-cyclic protograph-based Raptor-like LDPC codes for short block-lengths. - Sudarsan V. S. Ranganathan; Dariush Divsalar; Richard D. Wesel (ISIT, 2017)

Approaching capacity using incremental redundancy without feedback. - Haobo Wang; Sudarsan V. S. Ranganathan; Richard D. Wesel (ISIT, 2017)

An information density approach to analyzing and optimizing incremental redundancy with feedback. - Haobo Wang; Nathan Wong; Alexander M. Baldauf; Christopher K. Bachelor; Sudarsan V. S. Ranganathan; Dariush Divsalar; Richard D. Wesel (ISIT, 2017)

Sequential differential optimization of incremental redundancy transmission lengths: An example with tail-biting convolutional codes. - Nathan Wong; Kasra Vakilinia; Haobo Wang; Sudarsan V. S. Ranganathan; Richard D. Wesel (ITA, 2017)

Allocating Redundancy Between Erasure Coding and Channel Coding When Fading Channel Diversity Grows With Codeword Length. - Sudarsan V. S. Ranganathan; Tong Mu; Richard D. Wesel (IEEE Trans. Commun., 2017)

Serial List Viterbi Decoding with CRC: Managing Errors, Erasures, and Complexity. - Hengjie Yang; Sudarsan V. S. Ranganathan; Richard D. Wesel (GLOBECOM, 2018)

Linear Rate-Compatible Codes with Degree-1 Extending Variable Nodes Under Iterative Decoding. - Sudarsan V. S. Ranganathan; Richard D. Wesel; Dariush Divsalar (ISIT, 2018)

Advances in Protograph-Based LDPC Codes and a Rate Allocation Problem. - Sudarsan Vasista Srinivasan Ranganathan (2018)

Decoding Flash Memory with Progressive Reads and Independent vs. Joint Encoding of Bits in a Cell. - Nathan Wong; Ethan Liang; Haobo Wang; Sudarsan V. S. Ranganathan; Richard D. Wesel (GLOBECOM, 2019)

Variable-Length Coding With Shared Incremental Redundancy: Design Methods and Examples. - Haobo Wang; Sudarsan V. S. Ranganathan; Richard D. Wesel (IEEE Trans. Commun., 2019)

Quasi-Cyclic Protograph-Based Raptor-Like LDPC Codes for Short Block-Lengths. - Sudarsan V. S. Ranganathan; Dariush Divsalar; Richard D. Wesel (IEEE Trans. Inf. Theory, 2019)