Parallel Algorithms for Finding the Most Vital Edge in Weighted Graphs. - Sudarshan Banerjee; Sanjeev Saxena (J. Parallel Distributed Comput., 1997)

Efficient search space exploration for HW-SW partitioning. - Sudarshan Banerjee; Nikil D. Dutt (CODES+ISSS, 2004)

FIFO power optimization for on-chip networks. - Sudarshan Banerjee; Nikil D. Dutt (ACM Great Lakes Symposium on VLSI, 2004)

Physically-aware HW-SW partitioning for reconfigurable architectures with partial dynamic reconfiguration. - Sudarshan Banerjee; Elaheh Bozorgzadeh; Nikil D. Dutt (DAC, 2005)

ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement. - Partha Biswas; Sudarshan Banerjee; Nikil D. Dutt; Laura Pozzi 001; Paolo Ienne (DATE, 2005)

Considering Run-Time Reconfiguration Overhead in Task Graph Transformations for Dynamically Reconfigurable Architectures. - Sudarshan Banerjee; Elaheh Bozorgzadeh; Nikil D. Dutt (FCCM, 2005)

PARLGRAN: parallelism granularity selection for scheduling task chains on dynamically reconfigurable architectures. - Sudarshan Banerjee; Elaheh Bozorgzadeh; Nikil D. Dutt (ASP-DAC, 2006)

Design space exploration of real-time multi-media MPSoCs with heterogeneous scheduling policies. - Minyoung Kim 002; Sudarshan Banerjee; Nikil D. Dutt; Nalini Venkatasubramanian (CODES+ISSS, 2006)

Minimizing peak power for application chains on architectures with partial dynamic reconfiguration. - Sudarshan Banerjee; Elaheh Bozorgzadeh; Juanjo Noguera; Nikil D. Dutt (FPT, 2006)

Performance and Energy Benefits of Instruction Set Extensions in an FPGA Soft Core. - Partha Biswas; Sudarshan Banerjee; Nikil D. Dutt; Paolo Ienne; Laura Pozzi 001 (VLSI Design, 2006)

Integrating Physical Constraints in HW-SW Partitioning for Architectures With Partial Dynamic Reconfiguration. - Sudarshan Banerjee; Elaheh Bozorgzadeh; Nikil D. Dutt (IEEE Trans. Very Large Scale Integr. Syst., 2006)

ISEGEN: an iterative improvement-based ISE generation technique for fast customization of processors. - Partha Biswas; Sudarshan Banerjee; Nikil D. Dutt; Laura Pozzi 001; Paolo Ienne (IEEE Trans. Very Large Scale Integr. Syst., 2006)

Selective Band width and Resource Management in Scheduling for Dynamically Reconfigurable Architectures. - Sudarshan Banerjee; Elaheh Bozorgzadeh; Nikil D. Dutt; Juanjo Noguera (DAC, 2007)

Energy-aware co-processor selection for embedded processors on FPGAs. - Amir Hossein Gholamipour; Elaheh Bozorgzadeh; Sudarshan Banerjee (ICCD, 2007)

Energy-aware cosynthesis of real-time multimedia applications on MPSoCs using heterogeneous scheduling policies. - Minyoung Kim 002; Sudarshan Banerjee; Nikil D. Dutt; Nalini Venkatasubramanian (ACM Trans. Embed. Comput. Syst., 2008)

Strip packing with precedence constraints and strip packing with release times. - John Augustine; Sudarshan Banerjee; Sandy Irani (Theor. Comput. Sci., 2009)

Exploiting Application Data-Parallelism on Dynamically Reconfigurable Architectures: Placement and Architectural Considerations. - Sudarshan Banerjee; Elaheh Bozorgzadeh; Nikil D. Dutt (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Bandwidth Management in Application Mapping for Dynamically Reconfigurable Architectures. - Sudarshan Banerjee; Elaheh Bozorgzadeh; Juanjo Noguera; Nikil D. Dutt (ACM Trans. Reconfigurable Technol. Syst., 2010)