Formal Verification of an Intel XScale Processor Model with Scoreboarding, Specialized Execution Pipelines, and Impress Data-Memory Exceptions. - Sudarshan K. Srinivasan; Miroslav N. Velev (MEMOCODE, 2003)

Combining data remapping and voltage/frequency scaling of second level memory for energy reduction in embedded systems. - Jun-Cheol Park; Vincent John Mooney III; Sudarshan K. Srinivasan (Microelectron. J., 2003)

Automatic Verification of Safety and Liveness for XScale-Like Processor Models Using WEB Refinements. - Panagiotis Manolios; Sudarshan K. Srinivasan (DATE, 2004)

A Parameterized Benchmark Suite of Hard Pipelined-Machine-Verification Problems. - Panagiotis Manolios; Sudarshan K. Srinivasan (CHARME, 2005)

Refinement Maps for Efficient Verification of Processor Models. - Panagiotis Manolios; Sudarshan K. Srinivasan (DATE, 2005)

Verification of executable pipelined machines with bit-level interfaces. - Panagiotis Manolios; Sudarshan K. Srinivasan (ICCAD, 2005)

A complete compositional reasoning framework for the efficient verification of pipelined machines. - Panagiotis Manolios; Sudarshan K. Srinivasan (ICCAD, 2005)

A computationally ef cient method based on commitment re nement maps for verifying pipelined machines. - Panagiotis Manolios; Sudarshan K. Srinivasan (MEMOCODE, 2005)

Monolithic verification of deep pipelines with collapsed flushing. - Roma Kane; Panagiotis Manolios; Sudarshan K. Srinivasan (DATE, 2006)

Automatic memory reductions for RTL model verification. - Panagiotis Manolios; Sudarshan K. Srinivasan; Daron Vroon 001 (ICCAD, 2006)

A Framework for Verifying Bit-Level Pipelined Machines Based on Automated Deduction and Decision Procedures. - Panagiotis Manolios; Sudarshan K. Srinivasan (J. Autom. Reason., 2006)

BAT: The Bit-Level Analysis Tool. - Panagiotis Manolios; Sudarshan K. Srinivasan; Daron Vroon 001 (CAV, 2007)

Efficient Verification of Bit-Level Pipelined Machines Using Refinement. - Sudarshan K. Srinivasan (2007)

Automatic verification of safety and liveness for pipelined machines using WEB refinement. - Panagiotis Manolios; Sudarshan K. Srinivasan (ACM Trans. Design Autom. Electr. Syst., 2008)

A Refinement-Based Compositional Reasoning Framework for Pipelined Machine Verification. - Panagiotis Manolios; Sudarshan K. Srinivasan (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Efficient Hardware Implementation of a New Pseudo-random Bit Sequence Generator. - Raj S. Katti; Sudarshan K. Srinivasan (ISCAS, 2009)

Verification of Desynchronized Circuits. - Sudarshan K. Srinivasan; Raj S. Katti (ISCAS, 2009)

Verification of Synchronous Elastic Processors. - Sudarshan K. Srinivasan; Koushik Sarker; Rajendra S. Katti (IEEE Embed. Syst. Lett., 2009)

Token-Aware Completion Functions for Elastic Processor Verification. - Sudarshan K. Srinivasan; Koushik Sarker; Rajendra S. Katti (J. Electr. Comput. Eng., 2009)

Verifying Pipelines with BAT. - Panagiotis Manolios; Sudarshan K. Srinivasan (Design and Verification of Microprocessor Systems for High-Assurance Applications, 2010)

Joint optimal placement of PMU and conventional measurements in power systems. - Rajesh Kavasseri; Sudarshan K. Srinivasan (ISCAS, 2010)

Optimization Techniques for Verification of Out-of-Order Execution Machines. - Sudarshan K. Srinivasan (J. Electr. Comput. Eng., 2010)

Automatic Refinement Checking of Pipelines with Out-of-Order Execution. - Sudarshan K. Srinivasan (IEEE Trans. Computers, 2010)

Desynchronization: design for verification. - Sudarshan K. Srinivasan; Raj S. Katti (FMCAD, 2011)

On the Security of Randomized Arithmetic Codes Against Ciphertext-Only Attacks. - Raj S. Katti; Sudarshan K. Srinivasan; Aida Vosoughi (IEEE Trans. Inf. Forensics Secur., 2011)

Refinement-based verification of elastic pipelined systems. - Sudarshan K. Srinivasan; Y. Cai; Koushik Sarker (IET Comput. Digit. Tech., 2012)

Equivalence checking for synchronous elastic circuits. - Vidura Wijaysekara; Sudarshan K. Srinivasan (MEMOCODE, 2013)

Modeling and Analysis of State-of-the-art VM-based Cloud Management Platforms. - Saif Ur Rehman Malik; Samee U. Khan; Sudarshan K. Srinivasan (IEEE Trans. Cloud Comput., 2013)

Equivalence verification for NULL Convention Logic (NCL) circuits. - Vidura Wijayasekara; Sudarshan K. Srinivasan; Scott C. Smith (ICCD, 2014)

Timed Refinement for Verification of Real-Time Object Code Programs. - Mohana Asha Latha Dubasi; Sudarshan K. Srinivasan; Vidura Wijayasekara (VSTTE, 2014)

A Formal Verification Methodology for FPGA-Based Stepper Motor Control. - Shaista Jabeen; Sudarshan K. Srinivasan; Sana Shuja; Mohana Asha Latha Dubasi (IEEE Embed. Syst. Lett., 2015)

A Formal Verification Methodology for DDD Mode Pacemaker Control Programs. - Sana Shuja; Sudarshan K. Srinivasan; Shaista Jabeen; Dharmakeerthi Nawarathna (J. Electr. Comput. Eng., 2015)

Formal modeling and verification for pre-charge half buffer gates and circuits. - Ashiq A. Sakib; Scott C. Smith; Sudarshan K. Srinivasan (MWSCAS, 2017)

Formal verification methodology for real-time Field Programmable Gate Array. - Shaista Jabeen; Sudarshan K. Srinivasan; Sana Shuja (IET Comput. Digit. Tech., 2017)

An Equivalence Verification Methodology for Combinational Asynchronous PCHB Circuits. - Ashiq A. Sakib; Scott C. Smith; Sudarshan K. Srinivasan (MWSCAS, 2018)

IoT-Based Secure Embedded Scheme for Insulin Pump Data Acquisition and Monitoring. - Zeyad A. Al-Odat; Sudarshan K. Srinivasan; Eman Al-qtiemat; Mohana Asha Latha Dubasi; Sana Shuja (CoRR, 2018)

An Equivalence Verification Methodology for Asynchronous Sleep Convention Logic Circuits. - Mousam Hossain; Ashiq A. Sakib; Sudarshan K. Srinivasan; Scott C. Smith (ISCAS, 2019)

A Reliable IoT-Based Embedded Health Care System for Diabetic Patients. - Zeyad A. Al-Odat; Sudarshan K. Srinivasan; Eman M. Al-Qtiemat; Sana Shuja (CoRR, 2019)

Formal Modeling and Verification of PCHB Asynchronous Circuits. - Ashiq A. Sakib; Scott C. Smith; Sudarshan K. Srinivasan (IEEE Trans. Very Large Scale Integr. Syst., 2019)

A Formal Verification Approach for Detecting Opcode Trojans. - Nimish Mathure; Sudarshan K. Srinivasan; Kushal K. Ponugoti; Akansha Malik; Samuel Quanbeck (ICECS, 2020)

Hardware Trojan Design and Detection in Asynchronous NCL Circuits. - Kushal K. Ponugoti; Sudarshan K. Srinivasan; Scott C. Smith (ICECS, 2020)

Exploiting Dual-Rail Register Invariants for Equivalence Verification of NCL Circuits. - Son N. Le; Sudarshan K. Srinivasan; Scott C. Smith (MWSCAS, 2020)

Formal Verification of Completion-Completeness for NCL Circuits. - Son N. Le; Sudarshan K. Srinivasan; Scott C. Smith (MWSCAS, 2020)

Improved Efficiency of Object Code Verification Using Statically Abstracted Object Code. - N. Shaukat; Sana Shuja; Sudarshan K. Srinivasan; Shaista Jabeen (Sci. Program., 2020)

Formal Verification Approach to Detect Always-On Denial of Service Trojans in Pipelined Circuits. - Kushal K. Ponugoti; Sudarshan K. Srinivasan; Nimish Mathure (ICECS, 2021)

A Refinement-Based Approach to Spectre Invulnerability Verification. - Nimish Mathure; Sudarshan K. Srinivasan; Kushal K. Ponugoti (IEEE Access, 2022)

Illegal Trojan design and detection in asynchronous NULL Convention Logic and Sleep Convention Logic circuits. - Kushal K. Ponugoti; Sudarshan K. Srinivasan; Scott C. Smith; Nimish Mathure (IET Comput. Digit. Tech., 2022)

Hardware Mitigation and Verification For Rogue In-Flight Data Load Attacks. - Nimish Mathure; Sudarshan K. Srinivasan; Kushal K. Ponugoti; Arun Govindankutty (ICECS, 2023)

Verification of serialising instructions for security against transient execution attacks. - Kushal K. Ponugoti; Sudarshan K. Srinivasan; Nimish Mathure (IET Comput. Digit. Tech., 2023)

Rotational abstractions for verification of quantum Fourier transform circuits. - Arun Govindankutty; Sudarshan K. Srinivasan; Nimish Mathure (IET Quantum Commun., 2023)

Formal Verification For Cyclic Quantum Walk Circuits. - Benedicto James Sitou Campbell; Sudarshan K. Srinivasan (ISCAS, 2024)