High speed I/O and thermal effect characterization of 3D stacked ICs. - Moishe Groger; Shadi M. Harb; Devin Morris; William R. Eisenstadt; Sudeep Puligundla (3DIC, 2009)

Validating the performance of a 32nm CMOS high speed serial link receiver with adaptive equalization and baud-rate clock data recovery. - Sudeep Puligundla; Fulvio Spagna; Lidong Chen; Amanda Tran (ITC, 2010)

Comparison of hardware based and software based stress testing of memory IO interface. - Bruce Querbach; Sudeep Puligundla; Daniel Becerra; Zale T. Schoenborn; Patrick Chiang 001 (MWSCAS, 2013)

Platform IO and system memory test using L3 cache based test (CBT) and parallel execution of CPGC Intel BIST engine. - Bruce Querbach; Tan Peter Yanyang; Lovelace Van; David Blankenbeckler; Rahul Khanna; Sudeep Puligundla; Patrick Chiang 001 (ITC, 2015)

Architecture of a Reusable BIST Engine for Detection and Autocorrection of Memory Failures and for IO Debug, Validation, Link Training, and Power Optimization on 14-nm SoC. - Bruce Querbach; Rahul Khanna; Sudeep Puligundla; David Blankenbeckler; Joseph Crop; Patrick Yin Chiang (IEEE Des. Test, 2016)