A Construction for Convolutional Codes Using Block Codes - Sudhakar M. Reddy; John P. Robinson (Inf. Control., 1968)

Further Results on Convolutional Codes Derived from Block Codes - Sudhakar M. Reddy (Inf. Control., 1968)

A Decoding Algorithm for Some Convolutional Codes Constructed from Block Codes - Sudhakar M. Reddy; John P. Robinson (Inf. Control., 1968)

A feedback decoding scheme for linear convolutional codes (Corresp.). - Sudhakar M. Reddy (IEEE Trans. Inf. Theory, 1969)

A note on decoding of block codes (Corresp.). - Sudhakar M. Reddy (IEEE Trans. Inf. Theory, 1969)

Circulant bases for cyclic codes (Corresp.). - Charles W. Hoffner II; Sudhakar M. Reddy (IEEE Trans. Inf. Theory, 1970)

On decoding iterated codes. - Sudhakar M. Reddy (IEEE Trans. Inf. Theory, 1970)

A Class of High-Rate Double-Error-Correcting Convolutional Codes - Sudhakar M. Reddy; George I. Davida; John P. Robinson (Inf. Control., 1970)

Linear Convolutional Codes for Compound Channels - Sudhakar M. Reddy (Inf. Control., 1971)

Multiple Faults in Reed-Muller Canonic Networks - Kewal K. Saluja; Sudhakar M. Reddy (SWAT, 1972)

Multiple Fault Detection in Combinational Networks. - James W. Gault; John P. Robinson; Sudhakar M. Reddy (IEEE Trans. Computers, 1972)

Error-Control Techniques for Logic Processors. - Dhiraj K. Pradhan; Sudhakar M. Reddy (IEEE Trans. Computers, 1972)

Easily Testable Realizations ror Logic Functions. - Sudhakar M. Reddy (IEEE Trans. Computers, 1972)

A Design Procedure for Fault-Locatable Switching Circuits. - Sudhakar M. Reddy (IEEE Trans. Computers, 1972)

On block codes with specified maximum distance (Corresp.). - Sudhakar M. Reddy (IEEE Trans. Inf. Theory, 1972)

Random error and burst correction by iterated codes. - Sudhakar M. Reddy; John P. Robinson (IEEE Trans. Inf. Theory, 1972)

Hybrid block- self-orthogonal convolutional codes. - Sudhakar M. Reddy; John P. Robinson (IEEE Trans. Inf. Theory, 1972)

New binary codes. - Neil J. A. Sloane; Sudhakar M. Reddy; Chin-Long Chen (IEEE Trans. Inf. Theory, 1972)

Forward-Error Correction with Decision Feedback - George I. Davida; Sudhakar M. Reddy (Inf. Control., 1972)

Fault-Tolerant Asynchronous Networks. - Dhiraj K. Pradhan; Sudhakar M. Reddy (IEEE Trans. Computers, 1973)

Complete Test Sets for Logic Functions. - Sudhakar M. Reddy (IEEE Trans. Computers, 1973)

A (48, 31, 8) linear code (Corresp.). - V. V. Rao; Sudhakar M. Reddy (IEEE Trans. Inf. Theory, 1973)

On the Design of Logic Networks with Redundancy and Testability Considerations. - Ramaswami Dandapani; Sudhakar M. Reddy (IEEE Trans. Computers, 1974)

Authors' Reply. - James W. Gault; John P. Robinson; Sudhakar M. Reddy (IEEE Trans. Computers, 1974)

Design of Two-Level Fault-Tolerant Networks. - Dhiraj K. Pradhan; Sudhakar M. Reddy (IEEE Trans. Computers, 1974)

Note on Self-Checking Checkers. - Sudhakar M. Reddy (IEEE Trans. Computers, 1974)

Easily Testable Cellular Realizations for the (Exactly P)-out-of n and (p or More)-out-of n Logic Functions. - Sudhakar M. Reddy; James R. Wilson (IEEE Trans. Computers, 1974)

On Minimally Testable Logic Networks. - Kewal K. Saluja; Sudhakar M. Reddy (IEEE Trans. Computers, 1974)

Easily Testable Two-Dimensional Cellular Logic Arrays. - Kewal K. Saluja; Sudhakar M. Reddy (IEEE Trans. Computers, 1974)

Further results on decoders for Q -ary output channels (Corresp.). - Sudhakar M. Reddy (IEEE Trans. Inf. Theory, 1974)

Fault Detecting Test Sets for Reed-Muller Canonic Networks. - Kewal K. Saluja; Sudhakar M. Reddy (IEEE Trans. Computers, 1975)

A Routing Algorithm for Computer Communication Networks. - Dong H. Chyung; Sudhakar M. Reddy (IEEE Trans. Commun., 1975)

Techniques to Construct (2, 1) Separating Systems from Linear Error-Correcting Codes. - Dhiraj K. Pradhan; Sudhakar M. Reddy (IEEE Trans. Computers, 1976)

On Totally Self-Checking Checkers for Separable Codes. - Mohammad Javad Ashjaee; Sudhakar M. Reddy (IEEE Trans. Computers, 1977)

A Note on Testing Logic Circuits by Transition Counting. - Sudhakar M. Reddy (IEEE Trans. Computers, 1977)

Comments on "Minimal Fault Tests for Combinational Networks". - Sudhakar M. Reddy (IEEE Trans. Computers, 1977)

A Multicode Single Transition-Time State Assignment for Asynchronous Sequential Machines. - Jon G. Kuhl; Sudhakar M. Reddy (IEEE Trans. Computers, 1978)

On the Detection of Terminal Stuck-Faults. - Jon G. Kuhl; Sudhakar M. Reddy (IEEE Trans. Computers, 1978)

A Class of Linear Codes for Error Control in Byte-per-Card Organized Digital Systems. - Sudhakar M. Reddy (IEEE Trans. Computers, 1978)

Distributed Fault-Tolerance For Large Multiprocessor Systems. - Jon G. Kuhl; Sudhakar M. Reddy (ISCA, 1980)

Test Procedures for a Class of Pattern-Sensitive Faults in Semiconductor Random-Access Memories. - Dong S. Suk; Sudhakar M. Reddy (IEEE Trans. Computers, 1980)

A Testable Design of Iterative Logic Arrays. - R. Parthasarathy; Sudhakar M. Reddy (IEEE Trans. Computers, 1981)

A March Test for Functional Faults in Semiconductor Random Access Memories. - Dong S. Suk; Sudhakar M. Reddy (IEEE Trans. Computers, 1981)

Design of Easily Testable Microprocessors : A Case Study. - Sunil Nanda; Sudhakar M. Reddy (ITC, 1982)

A Fault-Tolerant Communication Architecture for Distributed Systems. - Dhiraj K. Pradhan; Sudhakar M. Reddy (IEEE Trans. Computers, 1982)

A Class of Graphs for Processor Interconnection. - Jon G. Kuhl; Sudhakar M. Reddy; P. Raghavan (ICPP, 1983)

On Testable Design for CMOS Logic Circuits. - Jon G. Kuhl; Sudhakar M. Reddy (ITC, 1983)

A gate level model for CMOS combinational logic circuits with application to fault detection. - Sudhakar M. Reddy; Vishwani D. Agrawal; Sunil K. Jain (DAC, 1984)

A Class of Graphs for Fault-Tolerant Processor Interconnections. - Vijay P. Kumar; Sudhakar M. Reddy (ICDCS, 1984)

On CMOS Totally Self-Checking Circuits. - Sridhar R. Manthani; Sudhakar M. Reddy (ITC, 1984)

A Diagnosis Algorithm for Distributed Computing Systems with Dynamic Failure and Repair. - Seyed H. Hosseini; Jon G. Kuhl; Sudhakar M. Reddy (IEEE Trans. Computers, 1984)

Transistor level test generation for MOS circuits. - Madhukar K. Reddy; Sudhakar M. Reddy; Prathima Agrawal (DAC, 1985)

On Multipath Multistage Interconnection Networks. - Sudhakar M. Reddy; Vijay P. Kumar (ICDCS, 1985)

Design and Analysis of Fault-Tolerant Multistage Interconnection Networks With Low Link Complexity. - Vijay P. Kumar; Sudhakar M. Reddy (ISCA, 1985)

On the Design of Testable Domino PLAs. - Dong Sam Ha; Sudhakar M. Reddy (ITC, 1985)

On the Design of Random Pattern Testable PLAs. - Dong Sam Ha; Sudhakar M. Reddy (ITC, 1986)

Fault-Tolerance Considerations in Large Multiple-Processor Systems. - Jon G. Kuhl; Sudhakar M. Reddy (Computer, 1986)

Detecting FET Stuck-Open Faults in CMOS Latches and Flip-Flops. - Madhukar K. Reddy; Sudhakar M. Reddy (IEEE Des. Test, 1986)

Testable Realizations for FET Stuck-Open Faults CMOS Combinational Logic Circuits. - Sudhakar M. Reddy; Madhukar K. Reddy (IEEE Trans. Computers, 1986)

A Parallel PLA Minimization Program. - R. Galivanche; Sudhakar M. Reddy (DAC, 1987)

Augmented Shuffle-Exchange Multistage Interconnection Networks. - Vijay P. Kumar; Sudhakar M. Reddy (Computer, 1987)

Scan Design Using Standard Flip-Flops. - Sudhakar M. Reddy; Ramaswami Dandapani (IEEE Des. Test, 1987)

Distributed Fault-Tolerance of Tree Structures. - Seyed H. Hosseini; Jon G. Kuhl; Sudhakar M. Reddy (IEEE Trans. Computers, 1987)

A New Approach to the Design of Testable PLA's. - Sudhakar M. Reddy; Dong Sam Ha (IEEE Trans. Computers, 1987)

On Delay Fault Testing in Logic Circuits. - Chin Jen Lin; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987)

On the design of robust testable CMOS combinational logic circuits. - Sandip Kundu; Sudhakar M. Reddy (FTCS, 1988)

On the design of robust multiple fault testable CMOS combinational logic circuits. - Sandip Kundu; Sudhakar M. Reddy; Niraj K. Jha (ICCAD, 1988)

On the Detection of Delay Faults. - Ankan K. Pramanick; Sudhakar M. Reddy (ITC, 1988)

On the Design of Pseudoexhaustive Testable PLA's. - Dong Sam Ha; Sudhakar M. Reddy (IEEE Trans. Computers, 1988)

On Self-Fault Diagnosis of the Distributed Systems. - Seyed H. Hosseini; Jon G. Kuhl; Sudhakar M. Reddy (IEEE Trans. Computers, 1988)

A Data Compression Technique for Built-In Self-Test. - Sudhakar M. Reddy; Kewal K. Saluja; Mark G. Karpovsky (IEEE Trans. Computers, 1988)

On the Repair of Redundant RAMs. - V. G. Hemmady; Sudhakar M. Reddy (DAC, 1989)

On the computation of the ranges of detected delay fault sizes. - Ankan K. Pramanick; Sudhakar M. Reddy (ICCAD, 1989)

Design of TSC checkers for implementation in CMOS technology. - Sandip Kundu; Sudhakar M. Reddy (ICCD, 1989)

A test generation system for path delay faults. - Srinivas Patil; Sudhakar M. Reddy (ICCD, 1989)

On the Design of Fault-Tolerant Two-Dimensional Systolic Arrays for Yield Enhancement. - Jung Hwan Kim; Sudhakar M. Reddy (IEEE Trans. Computers, 1989)

On path selection in combinational logic circuits. - Wing Ning Li; Sudhakar M. Reddy; Sartaj K. Sahni (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989)

On the fault coverage of delay fault detecting tests. - Ankan K. Pramanick; Sudhakar M. Reddy (EURO-DAC, 1990)

Zero aliasing compression. - Sandeep K. Gupta 001; Dhiraj K. Pradhan; Sudhakar M. Reddy (FTCS, 1990)

On the design of path delay fault testable combinational circuits. - Ankan K. Pramanick; Sudhakar M. Reddy (FTCS, 1990)

On Determining Scan Flip-Flops in Partial-Scan Designs. - Dong-Ho Lee; Sudhakar M. Reddy (ICCAD, 1990)

Embedded Totally Self-Checking Checkers: A Practical Design. - Sandip Kundu; Sudhakar M. Reddy (IEEE Des. Test Comput., 1990)

Robust tests for parity trees. - Sandip Kundu; Sudhakar M. Reddy (J. Electron. Test., 1990)

On Symmetric Error Correcting and All Unidirectional Error Detecting Codes. - Sandip Kundu; Sudhakar M. Reddy (IEEE Trans. Computers, 1990)

Long and short covering edges in combination logic circuits. - Wing Ning Li; Sudhakar M. Reddy; Sartaj Sahni (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990)

On Achieving a Complete Fault Coverage for Sequential Machines Using the Transition Fault Model. - Irith Pomeranz; Sudhakar M. Reddy (DAC, 1991)

Test Generation for Synchronous Sequential Circuits Using Multiple Observation Times. - Irith Pomeranz; Sudhakar M. Reddy (FTCS, 1991)

A New Test Generation Method for Sequential Circuits. - Dong-Ho Lee; Sudhakar M. Reddy (ICCAD, 1991)

Test Generation for Synchronous Sequential Circuits Based on Fault Extraction. - Irith Pomeranz; Sudhakar M. Reddy (ICCAD, 1991)

Increasing Fault Coverage for Synchronous Sequential Circuits by the Multiple Observation Time Test Strategy. - Irith Pomeranz; Sudhakar M. Reddy; Lakshmi N. Reddy (ICCAD, 1991)

Testing of Fault-Tolerant Hardware. - Irith Pomeranz; Sudhakar M. Reddy (Fault-Tolerant Computing Systems, 1991)

Achieving Complete Delay Fault Testability by Extra Inputs. - Irith Pomeranz; Sudhakar M. Reddy (ITC, 1991)

COMPACTEST: A Method to Generate Compact Test Sets for Combinatorial Circuits. - Irith Pomeranz; Lakshmi N. Reddy; Sudhakar M. Reddy (ITC, 1991)

On Multiple Path Propagating Tests for Path Delay Faults. - Ankan K. Pramanick; Sudhakar M. Reddy (ITC, 1991)

Design of robustly testable combinational logic circuits. - Sandip Kundu; Sudhakar M. Reddy; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991)

On Efficient Concurrent Fault Simulation for Synchronous Sequential Circuits. - Dong-Ho Lee; Sudhakar M. Reddy (DAC, 1992)

At-Speed Delay Testing of Synchronous Sequential Circuits. - Irith Pomeranz; Sudhakar M. Reddy (DAC, 1992)

SPADES: a simulator for path delay faults in sequential circuits. - Irith Pomeranz; Lakshmi N. Reddy; Sudhakar M. Reddy (EURO-DAC, 1992)

Synthesis of Multi-Level Combinational Circuits for Complete Robust Path Delay Fault Testability. - Niraj K. Jha; Irith Pomeranz; Sudhakar M. Reddy; Robert J. Miller (FTCS, 1992)

A Divide-And-Conquer Approach to Test Generation for Large Synchronous Sequential Circuits. - Irith Pomeranz; Sudhakar M. Reddy (FTCS, 1992)

On the generation of small dictionaries for fault location. - Irith Pomeranz; Sudhakar M. Reddy (ICCAD, 1992)

An efficient non-enumerative method to estimate path delay fault coverage. - Irith Pomeranz; Sudhakar M. Reddy (ICCAD, 1992)

COMPACTEST-II: a method to generate compact two-pattern test sets for combinational logic circuits. - Lakshmi N. Reddy; Irith Pomeranz; Sudhakar M. Reddy (ICCAD, 1992)

3-Weight Pseudo-Random Test Generation Based on a Deterministic Test Set. - Irith Pomeranz; Sudhakar M. Reddy (VLSI Design, 1992)

Generalization of independent faults for transition faults. - Irith Pomeranz; Sudhakar M. Reddy (VTS, 1992)

On the design of random pattern testable PLA based on weighted random pattern testing. - Dong Sam Ha; Sudhakar M. Reddy (J. Electron. Test., 1992)

The Multiple Observation Time Test Strategy. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Computers, 1992)

Guaranteed convergence in a class of Hopfield networks. - Yash Shrivastava; Soura Dasgupta; Sudhakar M. Reddy (IEEE Trans. Neural Networks, 1992)

INCREDYBLE-TG: INCREmental DYnamic test generation based on LEarning. - Irith Pomeranz; Sudhakar M. Reddy (DAC, 1993)

NEST: A Non-Enumerative Test Generation Method for Path Delay Faults in Combinational Circuits. - Irith Pomeranz; Sudhakar M. Reddy; Prasanti Uppaluri (DAC, 1993)

A method for diagnosing implementation errors in synchronous sequential circuits and its implications on synthesis. - Irith Pomeranz; Sudhakar M. Reddy (EURO-DAC, 1993)

EXOP (Extended Operation): A New Logical Fault Model for Digital Circuits. - Irith Pomeranz; Sudhakar M. Reddy (FTCS, 1993)

Design and Synthesis for Testability of Synchronous Sequential Circuits Based on Strong-Connectivity. - Irith Pomeranz; Sudhakar M. Reddy (FTCS, 1993)

Theory and Practice of Sequential Machine Testing and Testability. - Irith Pomeranz; Sudhakar M. Reddy; Janak H. Patel (FTCS, 1993)

Test generation for path delay faults based on learning. - Irith Pomeranz; Sudhakar M. Reddy (ICCAD, 1993)

On diagnosis and correction of design errors. - Irith Pomeranz; Sudhakar M. Reddy (ICCAD, 1993)

A Learning-Based Method to Match a Test Pattern Generator to a Circuit-Under-Test. - Irith Pomeranz; Sudhakar M. Reddy (ITC, 1993)

Heuristics for the Placement of Flip-Flops in Partial Scan Designs and the Placement of Signal Boosters in Lossy Circuits. - Doowon Paik; Sudhakar M. Reddy; Sartaj Sahni (VLSI Design, 1993)

On the Generation of Weights for Weighted Pseudo Random Testing. - Irith Pomeranz; Sudhakar M. Reddy (VLSI Design, 1993)

On Unified Delay Fault Testing. - Ankan K. Pramanick; Sudhakar M. Reddy (VLSI Design, 1993)

Genetic Beam Search for Gate Matrix Layout. - Khushro Shahookar; W. Khamisani; Pinaki Mazumder; Sudhakar M. Reddy (VLSI Design, 1993)

Classification of Faults in Synchronous Sequential Circuits. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Computers, 1993)

Testing of Fault-Tolerant Hardware Through Partial Control of Inputs. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Computers, 1993)

3-weight pseudo-random test generation based on a deterministic test set for combinational and sequential circuits. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

COMPACTEST: a method to generate compact test sets for combinational circuits. - Irith Pomeranz; Lakshmi N. Reddy; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

Design-for-Testability for Path Delay Faults in Large Combinatorial Circuits Using Test-Points. - Irith Pomeranz; Sudhakar M. Reddy (DAC, 1994)

On Improving Fault Diagnosis for Synchronous Sequential Circuits. - Irith Pomeranz; Sudhakar M. Reddy (DAC, 1994)

On Codeword Testing of Two-Rail and Parity TSC Checkers. - Sudhakar M. Reddy; Irith Pomeranz; Rahul Jain 014 (FTCS, 1994)

Test Pattern Generation for Path Delay Faults in Synchronous Sequential Circuits Using Multiple Fast Clocks and Multiple Observations Times. - Prasanti Uppaluri; Irith Pomeranz; Sudhakar M. Reddy (FTCS, 1994)

On testing delay faults in macro-based combinational circuits. - Irith Pomeranz; Sudhakar M. Reddy (ICCAD, 1994)

A Hierarchical Environment for Interactive Test Engineering. - Thomas Burch; Joachim Hartmann; Günter Hotz; M. Krallmann; U. Nikolaus; Sudhakar M. Reddy; Uwe Sparmann (ITC, 1994)

On Achieving Complete Testability of Synchronous Sequential Circuits with Synchronizing Sequences. - Irith Pomeranz; Sudhakar M. Reddy (ITC, 1994)

On compacting test sets by addition and removal of test vectors. - Seiji Kajihara; Irith Pomeranz; Kozo Kinoshita; Sudhakar M. Reddy (VTS, 1994)

On identifying undetectable and redundant faults in synchronous sequential circuits. - Irith Pomeranz; Sudhakar M. Reddy (VTS, 1994)

Deleting Vertices to Bound Path Length. - Doowon Paik; Sudhakar M. Reddy; Sartaj Sahni (IEEE Trans. Computers, 1994)

Application of Homing Sequences to Synchronous Sequential Circuit Testing. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Computers, 1994)

On the Role of Hardware Reset in Synchronous Sequential Circuit Test Generation. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Computers, 1994)

An efficient nonenumerative method to estimate the path delay fault coverage in combinational circuits. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

SPADES-ACE: a simulator for path delay faults in sequential circuits with extensions to arbitrary clocking schemes. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

On achieving complete fault coverage for sequential machines. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

On determining symmetries in inputs of logic circuits. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

Static compaction for two-pattern test sets. - Irith Pomeranz; Sudhakar M. Reddy (Asian Test Symposium, 1995)

On Synthesis-for-Testability of Combinational Logic Circuits. - Irith Pomeranz; Sudhakar M. Reddy (DAC, 1995)

Fast Identification of Robust Dependent Path Delay Faults. - Uwe Sparmann; D. Luxenburger; Kwang-Ting Cheng; Sudhakar M. Reddy (DAC, 1995)

On generating compact test sequences for synchronous sequential circuits. - Irith Pomeranz; Sudhakar M. Reddy (EURO-DAC, 1995)

Testing-what's missing? An incomplete list of challenges. - Sudhakar M. Reddy (ICCD, 1995)

Correcting Unidirectional Errors with Nonpositive Hopfield Networks. - Soura Dasgupta; Yash Shrivastava; Sudhakar M. Reddy (ICNN, 1995)

Low-Complexity Fault Simulation under the Multiplie Observation Time Testing Approach. - Irith Pomeranz; Sudhakar M. Reddy (ITC, 1995)

MUSTC-Testing: Multi-Stage-Combinational Test scheduling at the Register-Transfer Level. - Sitaran Yadavalli; Irith Pomeranz; Sudhakar M. Reddy (VLSI Design, 1995)

Compact test generation for bridging faults under IDDQ testing. - Remata S. Reddy; Irith Pomeranz; Sudhakar M. Reddy; Seiji Kajihara (VTS, 1995)

Efficient multiple path propagating tests for delay faults. - Ankan K. Pramanick; Sudhakar M. Reddy (J. Electron. Test., 1995)

Aliasing Computation Using Fault Simulation with Fault Dropping. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Computers, 1995)

On Fault Simulation for Synchronous Sequential Circuits. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Computers, 1995)

INCREDYBLE: A New Search Strategy for Design Automation Problems with Applications to Testing. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Computers, 1995)

Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits. - Seiji Kajihara; Irith Pomeranz; Kozo Kinoshita; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

On correction of multiple design errors. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

NEST: a nonenumerative test generation method for path delay faults in combinational circuits. - Irith Pomeranz; Sudhakar M. Reddy; Prasanti Uppaluri (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

On Test Generation for Interconnected Finite-State Machines: The Input Sequence Propagation Problem. - Irith Pomeranz; Sudhakar M. Reddy (Asian Test Symposium, 1996)

Low-Complexity Fault Diagnosis Under the Multiple Observation Time Testing Approach. - Irith Pomeranz; Sudhakar M. Reddy (Asian Test Symposium, 1996)

"Challenges in Testing". - Sudhakar M. Reddy (Asian Test Symposium, 1996)

Minimal Delay Test Sets for Unate Gate Networks. - Uwe Sparmann; Holger Müller; Sudhakar M. Reddy (Asian Test Symposium, 1996)

On Static Compaction of Test Sequences for Synchronous Sequential Circuits. - Irith Pomeranz; Sudhakar M. Reddy (DAC, 1996)

A Fast Optimal Robust Path Delay Fault Testable Adder. - Bernd Becker 001; Rolf Drechsler; Rolf Krieger; Sudhakar M. Reddy (ED&TC, 1996)

On Test Generation for Interconnected Finite-State Machines - The Output Sequence Justification Problem. - Irith Pomeranz; Sudhakar M. Reddy (ED&TC, 1996)

Dynamic Test Compaction for Synchronous Sequential Circuits using Static Compaction Techniques. - Irith Pomeranz; Sudhakar M. Reddy (FTCS, 1996)

On Double Transition Faults as a Delay Fault Model. - Irith Pomeranz; Sudhakar M. Reddy; Janak H. Patel (Great Lakes Symposium on VLSI, 1996)

Perspectives for High Performance Computing in Workstation Networks. - Volker Strumpen; Balkrishna Ramkumar; Thomas L. Casavant; Sudhakar M. Reddy (HPCN Europe, 1996)

Fault Location Based on Circuit Partitioning. - Irith Pomeranz; Sudhakar M. Reddy (ICCD, 1996)

Local Transformations and Robust Dependent Path Delay. - Harry Hengster; Uwe Sparmann; Bernd Becker 001; Sudhakar M. Reddy (ITC, 1996)

On Cancelling the Effects of Logic Sharing for Improved Path Delay Fault Testability. - Irith Pomeranz; Sudhakar M. Reddy (ITC, 1996)

On Finding Functionally Identical and Functionally Opposite Lines in Combinational Logic Circuits. - Irith Pomeranz; Sudhakar M. Reddy (VLSI Design, 1996)

Delay Fault Testing: How Robust are Our Models? - Sandeep K. Gupta 001; Slawomir Pilarski; Sudhakar M. Reddy; Jacob Savir; Prab Varma (VTS, 1996)

On the effects of test compaction on defect coverage. - Sudhakar M. Reddy; Irith Pomeranz; Seiji Kajihara (VTS, 1996)

On Removing Redundancies from Synchronous Sequential Circuits with Synchronizing Sequences. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Computers, 1996)

On the Number of Tests to Detect All Path Delay Faults in Combinational Logic Circuits. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Computers, 1996)

A novel framework for logic verification in a synthesis environment. - Wolfgang Kunz; Dhiraj K. Pradhan; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

On the effectiveness of residue code checking for parallel two's complement multipliers. - Uwe Sparmann; Sudhakar M. Reddy (IEEE Trans. Very Large Scale Integr. Syst., 1996)

On the Compaction of Test Sets Produced by Genetic Optimization. - Irith Pomeranz; Sudhakar M. Reddy (Asian Test Symposium, 1997)

TEMPLATES: A Test Generation Procedure for Synchronous Sequential Circuits. - Irith Pomeranz; Sudhakar M. Reddy (Asian Test Symposium, 1997)

Fault Simulation under the Multiple Observation Time Approach using Backward Implications. - Irith Pomeranz; Sudhakar M. Reddy (DAC, 1997)

On improving genetic optimization based test generation. - Irith Pomeranz; Sudhakar M. Reddy (ED&TC, 1997)

On the use of reset to increase the testability of interconnected finite-state machines. - Irith Pomeranz; Sudhakar M. Reddy (ED&TC, 1997)

ACTIV-LOCSTEP: A Test Generation Procedure Based on Logic Simulation and Fault Activation. - Irith Pomeranz; Sudhakar M. Reddy (FTCS, 1997)

On Generating Test Sets that Remain Valid in the Presence of Undetected Faults. - Irith Pomeranz; Sudhakar M. Reddy (Great Lakes Symposium on VLSI, 1997)

Built-in test generation for synchronous sequential circuits. - Irith Pomeranz; Sudhakar M. Reddy (ICCAD, 1997)

Vector Restoration Based Static Compaction of Test Sequences for Synchronous Sequential Circuits. - Irith Pomeranz; Sudhakar M. Reddy (ICCD, 1997)

(Quasi-) Linear Path Delay Fault Tests for Adders. - Bernd Becker 001; Rolf Drechsler; Sudhakar M. Reddy (VLSI Design, 1997)

A Method for Identifying Robust Dependent and Functionally Unsensitizable Paths. - Seiji Kajihara; Kozo Kinoshita; Irith Pomeranz; Sudhakar M. Reddy (VLSI Design, 1997)

On the Detection of Reset Faults in Synchronous Sequential Circuits. - Irith Pomeranz; Sudhakar M. Reddy (VLSI Design, 1997)

On Full Reset as a Design-For-Testability Technique. - Irith Pomeranz; Sudhakar M. Reddy (VLSI Design, 1997)

EXTEST: a method to extend test sequences of synchronous sequential circuits to increase the fault coverage. - Irith Pomeranz; Sudhakar M. Reddy (VTS, 1997)

On n-detection test sequences for synchronous sequential circuits343. - Irith Pomeranz; Sudhakar M. Reddy (VTS, 1997)

Perspectives on high performance network computing. - Volker Strumpen; Balkrishna Ramkumar; Thomas L. Casavant; Sudhakar M. Reddy (Future Gener. Comput. Syst., 1997)

On Dictionary-Based Fault Location in Digital Logic Circuits. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Computers, 1997)

Test Generation for Multiple State-Table Faults in Finite-State Machines. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Computers, 1997)

LOCSTEP: a logic-simulation-based test generation procedure. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

On error correction in macro-based circuits. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

On the fault coverage of gate delay fault detecting tests. - Ankan K. Pramanick; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

Compact test sets for high defect coverage. - Sudhakar M. Reddy; Irith Pomeranz; Seiji Kajihara (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

On Speeding-Up Vector Restoration Based Static Compaction of Test Sequences for Sequential Circuits . - Ruifeng Guo; Irith Pomeranz; Sudhakar M. Reddy (Asian Test Symposium, 1998)

Test Generation for Synchronous Sequential Circuits to Reduce Storage Requirements. - Irith Pomeranz; Sudhakar M. Reddy (Asian Test Symposium, 1998)

Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits Based on Vector Restoration. - Ruifeng Guo; Irith Pomeranz; Sudhakar M. Reddy (DATE, 1998)

A Synthesis Procedure for Flexible Logic Functions. - Irith Pomeranz; Sudhakar M. Reddy (DATE, 1998)

Design-for-Testability for Synchronous Sequential Circuits using Locally Available Lines. - Irith Pomeranz; Sudhakar M. Reddy (DATE, 1998)

A Generalized Test Generation Procedure for Path Delay Faults. - Irith Pomeranz; Sudhakar M. Reddy (FTCS, 1998)

Test Compaction for Synchronous Sequential Circuits by Test Sequence Recycling. - Irith Pomeranz; Sudhakar M. Reddy (Great Lakes Symposium on VLSI, 1998)

On finding undetectable and redundant faults in synchronous sequential circuits. - Xijiang Lin; Irith Pomeranz; Sudhakar M. Reddy (ICCD, 1998)

Improved built-in test pattern generators based on comparison units for synchronous sequential circuits. - Irith Pomeranz; Sudhakar M. Reddy (ICCD, 1998)

A diagnostic test generation procedure for synchronous sequential circuits based on test elimination. - Irith Pomeranz; Sudhakar M. Reddy (ITC, 1998)

MIX: A Test Generation System for Synchronous Sequential Circuits. - Xijiang Lin; Irith Pomeranz; Sudhakar M. Reddy (VLSI Design, 1998)

On Test Compaction Objectives for Combinational and Sequential Circuits. - Irith Pomeranz; Sudhakar M. Reddy (VLSI Design, 1998)

On Removing Redundant Faults in Synchronous Sequential Circuits. - Xijiang Lin; Irith Pomeranz; Sudhakar M. Reddy (VTS, 1998)

On Synchronizing Sequences and Test Sequence Partitioning. - Irith Pomeranz; Sudhakar M. Reddy (VTS, 1998)

Stuck-At Tuple-Detection: A Fault Model Based on Stuck-At Faults for Improved Defect Coverage. - Irith Pomeranz; Sudhakar M. Reddy (VTS, 1998)

Vertex Splitting in Dags and Applications to Partial Scan Designs and Lossy Circuits. - Doowon Paik; Sudhakar M. Reddy; Sartaj Sahni (Int. J. Found. Comput. Sci., 1998)

Delay fault models for VLSI circuits1. - Irith Pomeranz; Sudhakar M. Reddy (Integr., 1998)

Location of Stuck-At Faults and Bridging Faults Based on Circuit Partitioning. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Computers, 1998)

Techniques for minimizing power dissipation in scan and combinational circuits during test application. - Vinay Dabholkar; Sreejit Chakravarty; Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

Low-complexity fault simulation under the multiple observation time and the restricted multiple observation time testing approaches. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

Design-for-testability for path delay faults in large combinational circuits using test points. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

Test sequences to achieve high defect coverage for synchronous sequential circuits. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

Functional test generation for delay faults in combinational circuits. - Irith Pomeranz; Sudhakar M. Reddy (ACM Trans. Design Autom. Electr. Syst., 1998)

On methods to match a test pattern generator to a circuit-under-test. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Very Large Scale Integr. Syst., 1998)

Vector-Based Functional Fault Models for Delay Faults. - Irith Pomeranz; Sudhakar M. Reddy (Asian Test Symposium, 1999)

Pattern Sensitivity: A Property to Guide Test Generation for Combinational Circuits. - Irith Pomeranz; Sudhakar M. Reddy (Asian Test Symposium, 1999)

Proptest: A Property Based Test Pattern Generator for Sequential Circuits Using Test Compaction. - Ruifeng Guo; Sudhakar M. Reddy; Irith Pomeranz (DAC, 1999)

Built-In Test Sequence Generation for Synchronous Sequential Circuits Based on Loading and Expansion of Test Subsequences. - Irith Pomeranz; Sudhakar M. Reddy (DAC, 1999)

Full Scan Fault Coverage With Partial Scan. - Xijiang Lin; Irith Pomeranz; Sudhakar M. Reddy (DATE, 1999)

On avoiding undetectable faults during test generation. - Irith Pomeranz; Sudhakar M. Reddy (ETW, 1999)

PASTA: Partial Scan to Enhance Test Compaction. - Irith Pomeranz; Sudhakar M. Reddy (Great Lakes Symposium on VLSI, 1999)

Techniques for improving the efficiency of sequential circuit test generation. - Xijiang Lin; Irith Pomeranz; Sudhakar M. Reddy (ICCAD, 1999)

An approach for improving the levels of compaction achieved by vector omission. - Irith Pomeranz; Sudhakar M. Reddy (ICCAD, 1999)

Fault Simulation Based Test Generation for Combinational Circuits Using Dynamically Selected Sub-Circuits. - Irith Pomeranz; Sudhakar M. Reddy (ICCD, 1999)

On achieving complete coverage of delay faults in full scan circuits using locally available lines. - Irith Pomeranz; Sudhakar M. Reddy (ITC, 1999)

Application of Tools Developed at the University of Iowa to ITC Benchmarks. - Sudhakar M. Reddy (ITC, 1999)

The effects of test compaction on fault diagnosis. - Yun Shao 002; Ruifeng Guo; Sudhakar M. Reddy; Irith Pomeranz (ITC, 1999)

SymSim: symbolic fault simulation of data-flow data-path designs at the Register-Transfer level. - Sitaran Yadavalli; Sudhakar M. Reddy (ITC, 1999)

VERSE: A Vector Replacement Procedure for Improving Test Compaction in Synchronous Sequential Circuits. - Irith Pomeranz; Sudhakar M. Reddy (VLSI Design, 1999)

A Fault Simulation Based Test Pattern Generator for Synchronous Sequential Circuits. - Ruifeng Guo; Irith Pomeranz; Sudhakar M. Reddy (VTS, 1999)

A Flexible Path Selection Procedure for Path Delay Fault Testing. - Irith Pomeranz; Sudhakar M. Reddy (VTS, 1999)

On n-Detection Test Sets and Variable n-Detection Test Sets for Transition Faults. - Irith Pomeranz; Sudhakar M. Reddy (VTS, 1999)

Procedures for Identifying Undetectable and Redundant Faults In Synchronous Sequential Circuits. - Sudhakar M. Reddy; Irith Pomeranz; Nadir Z. Basturkmen; Xijiang Lin (VTS, 1999)

A Cone-Based Genetic Optimization Procedure for Test Generation and Its Application to n-Detections in Combinational Circuits. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Computers, 1999)

A comment on "Improving a nonenumerative method to estimate path delay fault coverage". - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

Static test compaction for synchronous sequential circuits based on vector restoration. - Irith Pomeranz; Sudhakar M. Reddy; Ruifeng Guo (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

Universal delay test sets for logic networks. - Uwe Sparmann; Holger Müller; Sudhakar M. Reddy (IEEE Trans. Very Large Scale Integr. Syst., 1999)

High Performance/Delay Testing. - Shi-Yu Huang; Sudhakar M. Reddy (Asian Test Symposium, 2000)

Enhanced untestable path analysis using edge graphs. - Seiji Kajihara; Takashi Shimono; Irith Pomeranz; Sudhakar M. Reddy (Asian Test Symposium, 2000)

On the feasibility of fault simulation using partial circuit descriptions. - Irith Pomeranz; Sudhakar M. Reddy (Asian Test Symposium, 2000)

Reducing test application time for full scan circuits by the addition of transfer sequences. - Irith Pomeranz; Sudhakar M. Reddy (Asian Test Symposium, 2000)

On diagnosis of pattern-dependent delay faults. - Irith Pomeranz; Sudhakar M. Reddy (DAC, 2000)

Built-In Generation of Weighted Test Sequences for Synchronous Sequential Circuits. - Irith Pomeranz; Sudhakar M. Reddy (DATE, 2000)

Functional Test Generation for Full Scan Circuits. - Irith Pomeranz; Sudhakar M. Reddy (DATE, 2000)

Test-Point Insertion to Enhance Test Compaction for Scan Designs. - Irith Pomeranz; Sudhakar M. Reddy (DSN, 2000)

On the use of multiple fault detection times in a method for built-in test pattern generation for synchronous sequential circuits. - Irith Pomeranz; Sudhakar M. Reddy (ETW, 2000)

Improving the Proportion of At-Speed Tests in Scan BIST. - Yu Huang 005; Irith Pomeranz; Sudhakar M. Reddy; Janusz Rajski (ICCAD, 2000)

Simulation Based Test Generation for Scan Designs. - Irith Pomeranz; Sudhakar M. Reddy (ICCAD, 2000)

Sensitivity Levels of Test Patterns and Their Usefulness in Simulation-Based Test Generation. - Irith Pomeranz; Sudhakar M. Reddy (ICCD, 2000)

On Test Application Time and Defect Detection Capabilities of Test Sets for Scan Designs. - Irith Pomeranz; Sudhakar M. Reddy (ICCD, 2000)

Selection of potentially testable path delay faults for test generation. - Atsushi Murakami; Seiji Kajihara; Tsutomu Sasao; Irith Pomeranz; Sudhakar M. Reddy (ITC, 2000)

On validating data hold times for flip-flops in sequential circuits. - Sudhakar M. Reddy; Irith Pomeranz; Seiji Kajihara; Atsushi Murakami; Sadami Takeoka; Mitsuyasu Ohta (ITC, 2000)

Fault diagnosis based on parameters of output responses. - Irith Pomeranz; Sudhakar M. Reddy (PRDC, 2000)

Test Transformation to Improve Compaction by Statistical Encoding. - Hideyuki Ichihara; Kozo Kinoshita; Irith Pomeranz; Sudhakar M. Reddy (VLSI Design, 2000)

On Synchronizing Sequences and Unspecified Values in Output Responses of Synchronous Sequential Circuits. - Irith Pomeranz; Sudhakar M. Reddy (VLSI Design, 2000)

SIFAR: Static Test Compaction for Synchronous Sequential Circuits Based on Single Fault Restoration. - Xijiang Lin; Wu-Tung Cheng; Irith Pomeranz; Sudhakar M. Reddy (VTS, 2000)

Static Test Compaction for Scan-Based Designs to Reduce Test Application Time. - Irith Pomeranz; Sudhakar M. Reddy (J. Electron. Test., 2000)

On Finding a Minimal Functional Description of a Finite-State Machine for Test Generation for Adjacent Machines. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Computers, 2000)

On the Use of Fully Specified Initial States for Testing of Synchronous Sequential Circuits. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Computers, 2000)

Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Computers, 2000)

On n-detection test sets and variable n-detection test sets fortransition faults. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

A diagnostic test generation procedure based on test elimination byvector omission for synchronous sequential circuits. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

On synchronizable circuits and their synchronizing sequences. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

On Improving a Fault Simulation Based Test Generator for Synchronous Sequential Circuits. - Ruifeng Guo; Sudhakar M. Reddy; Irith Pomeranz (Asian Test Symposium, 2001)

Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SoC D. - Yu Huang 005; Wu-Tung Cheng; Chien-Chung Tsai; Nilanjan Mukherjee 001; Omer Samman; Yahya Zaidan; Sudhakar M. Reddy (Asian Test Symposium, 2001)

A Postprocessing Procedure to Reduce the Number of Different Test Lengths in a Test Set for Scan Circuits. - Irith Pomeranz; Sudhakar M. Reddy (Asian Test Symposium, 2001)

Experimental Results of Forward-Looking Reverse Order Fault Simulation on Industrial Circuits with Scan. - Irith Pomeranz; Sudhakar M. Reddy; Xijiang Lin (Asian Test Symposium, 2001)

An Efficient Method to Identify Untestable Path Delay Faults. - Yun Shao 002; Sudhakar M. Reddy; Seiji Kajihara; Irith Pomeranz (Asian Test Symposium, 2001)

Effect of RTL coding style on testability. - Yu Huang 005; Chien-Chung Tsai; Nilanjan Mukherhee; Wu-Tung Cheng; Sudhakar M. Reddy (CICC, 2001)

An Approach to Test Compaction for Scan Circuits that Enhances At-Speed Testing. - Irith Pomeranz; Sudhakar M. Reddy (DAC, 2001)

Sequence reordering to improve the levels of compaction achievable by static compaction procedures. - Irith Pomeranz; Sudhakar M. Reddy (DATE, 2001)

Definitions of the numbers of detections of target faults and their effectiveness in guiding test generation for high defect coverage. - Irith Pomeranz; Sudhakar M. Reddy (DATE, 2001)

ITEM: an iterative improvement test generation procedure for synchronous sequential circuits. - Irith Pomeranz; Sudhakar M. Reddy (ACM Great Lakes Symposium on VLSI, 2001)

Estimating the relative single stuck-at fault coverage of test sets for a combinational logic block from its functional description. - Irith Pomeranz; Sudhakar M. Reddy (HLDVT, 2001)

REDI: An Efficient Fault Oriented Procedure to Identify Redundant Faults in Combinational Logic Circuits. - Chen Wang 014; Irith Pomeranz; Sudhakar M. Reddy (ICCAD, 2001)

COREL: A Dynamic Compaction Procedure for Synchronous Sequential Circuits with Repetition and Local Static Compaction. - Irith Pomeranz; Sudhakar M. Reddy (ICCD, 2001)

A Partitioning and Storage Based Built-in Test Pattern Generation Method for Synchronous Sequential Circuits. - Irith Pomeranz; Sudhakar M. Reddy (ICCD, 2001)

On RTL scan design. - Yu Huang 005; Chien-Chung Tsai; Nilanjan Mukherjee 001; Omer Samman; Dan Devries; Wu-Tung Cheng; Sudhakar M. Reddy (ITC, 2001)

On static test compaction and test pattern ordering for scan designs. - Xijiang Lin; Janusz Rajski; Irith Pomeranz; Sudhakar M. Reddy (ITC, 2001)

A method to enhance the fault coverage obtained by output response comparison of identical circuits. - Irith Pomeranz; Sudhakar M. Reddy (ITC, 2001)

On Improving Static Test Compaction for Sequential Circuits. - Ruifeng Guo; Irith Pomeranz; Sudhakar M. Reddy (VLSI Design, 2001)

On the Use of Fault Dominance in n-Detection Test Generation. - Irith Pomeranz; Sudhakar M. Reddy (VTS, 2001)

Design-for-testability to achieve complete coverage of delay faults in standard full scan circuits. - Irith Pomeranz; Sudhakar M. Reddy (J. Syst. Archit., 2001)

Vector replacement to improve static-test compaction forsynchronous sequential circuits. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

On diagnosis and diagnostic test generation for pattern-dependenttransition faults. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

Forward-looking fault simulation for improved static compaction. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

A built-in self-test method for diagnosis of synchronous sequential circuits. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Very Large Scale Integr. Syst., 2001)

Resynthesis of combinational logic circuits for improved path delay fault testability using comparison units. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Very Large Scale Integr. Syst., 2001)

Core - Clustering Based SOC Test Scheduling Optimization. - Yu Huang 005; Sudhakar M. Reddy; Wu-Tung Cheng (Asian Test Symposium, 2002)

Test Data Compression Using Don?t-Care Identification and Statistical Encoding. - Seiji Kajihara; Kenjiro Taniguchi; Kohei Miyase; Irith Pomeranz; Sudhakar M. Reddy (Asian Test Symposium, 2002)

Improving the Efficiency of Static Compaction Based on Chronological Order Enumeration of Test Sequences. - Irith Pomeranz; Sudhakar M. Reddy (Asian Test Symposium, 2002)

A Partitioning and Storage Based Built-In Test Pattern Generation Method for Delay Faults in Scan Circuits. - Irith Pomeranz; Sudhakar M. Reddy (Asian Test Symposium, 2002)

On Generating High Quality Tests for Transition Faults. - Yun Shao 002; Irith Pomeranz; Sudhakar M. Reddy (Asian Test Symposium, 2002)

On output response compression in the presence of unknown output values. - Irith Pomeranz; Sandip Kundu; Sudhakar M. Reddy (DAC, 2002)

Finding a Common Fault Response for Diagnosis during Silicon Debug. - Irith Pomeranz; Janusz Rajski; Sudhakar M. Reddy (DATE, 2002)

Test Data Compression Using Don't-Care Identification and Statistical Encoding. - Seiji Kajihara; Kenjiro Taniguchi; Irith Pomeranz; Sudhakar M. Reddy (DELTA, 2002)

A Method of Static Test Compaction Based on Don't Care Identification. - Kohei Miyase; Seiji Kajihara; Sudhakar M. Reddy (DELTA, 2002)

Properties of Output Sequences and their Use in Guiding Property-Based Test Generation for Synchronous Sequential Circuits. - Irith Pomeranz; Sudhakar M. Reddy (DELTA, 2002)

On undetectable faults in partial scan circuits. - Irith Pomeranz; Sudhakar M. Reddy (ICCAD, 2002)

Conflict driven techniques for improving deterministic test pattern generation. - Chen Wang 014; Sudhakar M. Reddy; Irith Pomeranz; Xijiang Lin; Janusz Rajski (ICCAD, 2002)

Don't-Care Identification on Specific Bits of Test Patterns. - Kohei Miyase; Seiji Kajihara; Irith Pomeranz; Sudhakar M. Reddy (ICCD, 2002)

On the Coverage of Delay Faults in Scan Designs with Multiple Scan Chains. - Irith Pomeranz; Sudhakar M. Reddy (ICCD, 2002)

Pseudo Random Patterns Using Markov Sources for Scan BIST. - Nadir Z. Basturkmen; Sudhakar M. Reddy; Irith Pomeranz (ITC, 2002)

Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3-D Bin Packing Algorithm. - Yu Huang 005; Sudhakar M. Reddy; Wu-Tung Cheng; Paul Reuter; Nilanjan Mukherjee 001; Chien-Chung Tsai; Omer Samman; Yahya Zaidan (ITC, 2002)

On Testing of Interconnect Open Defects in Combinational Logic Circuits with Stems of Large Fanout. - Sudhakar M. Reddy; Irith Pomeranz; Huaxing Tang; Seiji Kajihara; Kozo Kinoshita (ITC, 2002)

Improved Algorithms for Constructive Multi-Phase Test Point Insertion for Scan Based BIST. - Nadir Z. Basturkmen; Sudhakar M. Reddy; Janusz Rajski (ASP-DAC/VLSI Design, 2002)

Constraint Driven Pin Mapping for Concurrent SOC Testing. - Yu Huang 005; Nilanjan Mukherjee 001; Chien-Chung Tsai; Omer Samman; Yahya Zaidan; Yanping Zhang; Wu-Tung Cheng; Sudhakar M. Reddy (ASP-DAC/VLSI Design, 2002)

A Partitioning and Storage Based Built-In Test Pattern Generation Method for Scan Circuits. - Irith Pomeranz; Sudhakar M. Reddy (ASP-DAC/VLSI Design, 2002)

Path Delay Fault Test Generation for Standard Scan Designs Using State Tuples. - Yun Shao 002; Irith Pomeranz; Sudhakar M. Reddy (ASP-DAC/VLSI Design, 2002)

On Concurrent Test of Core-Based SOC Design. - Yu Huang 005; Wu-Tung Cheng; Chien-Chung Tsai; Nilanjan Mukherjee 001; Omer Samman; Yahya Zaidan; Sudhakar M. Reddy (J. Electron. Test., 2002)

Synthesis of Scan Chains for Netlist Descriptions at RT-Level. - Yu Huang 005; Chien-Chung Tsai; Nilanjan Mukherjee 001; Omer Samman; Wu-Tung Cheng; Sudhakar M. Reddy (J. Electron. Test., 2002)

Built-In Test Sequence Generation for Synchronous Sequential Circuits Based on Loading and Expansion of Input Sequences Using Single and Multiple Fault Detection Times. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Computers, 2002)

Enumeration of Test Sequences in Increasing Chronological Order to Improve the Levels of Compaction Achieved by Vector Omission. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Computers, 2002)

A Storage-Based Built-In Test Pattern Generation Method for Scan Circuits Based on Partitioning and Reduction of a Precomputed Test Set. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Computers, 2002)

Property-based test generation for scan designs and the effects ofthe test application scheme and scan selection on the number ofdetectable faults. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

Test compaction for at-speed testing of scan circuits based onnonscan test. sequences and removal of transfer sequences. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

n-pass n-detection fault simulation and its applications. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

Testing Delay Faults in Embedded CAMs. - Xiaogang Du; Sudhakar M. Reddy; Joseph Rayhawk; Wu-Tung Cheng (Asian Test Symposium, 2003)

A DFT Approach for Path Delay Faults in Interconnected Circuits. - Irith Pomeranz; Sudhakar M. Reddy (Asian Test Symposium, 2003)

Test Data Volume Reduction by Test Data Realignment. - Irith Pomeranz; Sudhakar M. Reddy (Asian Test Symposium, 2003)

A scan BIST generation method using a markov source and partial bit-fixing. - Wei Li 023; Chaowen Yu; Sudhakar M. Reddy; Irith Pomeranz (DAC, 2003)

On test data compression and n-detection test sets. - Irith Pomeranz; Sudhakar M. Reddy (DAC, 2003)

Evolutionary Optimization of Markov Sources for Pseudo Random Scan BIST. - Ilia Polian; Bernd Becker 001; Sudhakar M. Reddy (DATE, 2003)

A New Approach to Test Generation and Test Compaction for Scan Circuits. - Irith Pomeranz; Sudhakar M. Reddy (DATE, 2003)

Test Data Compression Based on Output Dependence. - Irith Pomeranz; Sudhakar M. Reddy (DATE, 2003)

On the Characterization of Hard-to-Detect Bridging Faults. - Irith Pomeranz; Sudhakar M. Reddy; Sandip Kundu (DATE, 2003)

On path selection for delay fault testing considering operating conditions [logic IC testing]. - Bharath Seshadri; Irith Pomeranz; Sudhakar M. Reddy; Sandip Kundu (ETW, 2003)

On Application of Output Masking to Undetectable Faults in Synchronous Sequential Circuits with Design-for-Testability Logic. - Irith Pomeranz; Sudhakar M. Reddy (ICCAD, 2003)

On Compacting Test Response Data Containing Unknown Values. - Chen Wang 014; Sudhakar M. Reddy; Irith Pomeranz; Janusz Rajski; Jerzy Tyszer (ICCAD, 2003)

Procedures for Identifying Untestable and Redundant Transition Faults in Synchronous Sequential Circuits. - Gang Chen 011; Sudhakar M. Reddy; Irith Pomeranz (ICCD, 2003)

Static Test Compaction for Multiple Full-Scan Circuits. - Irith Pomeranz; Sudhakar M. Reddy (ICCD, 2003)

An Improved Markov Source Design for Scan BIST. - Chaowen Yu; Wei Li 023; Sudhakar M. Reddy; Irith Pomeranz (IOLTS, 2003)

Static Pin Mapping and SOC Test Scheduling for Cores with Multiple Test Sets. - Yu Huang 005; Wu-Tung Cheng; Chien-Chung Tsai; Nilanjan Mukherjee 001; Sudhakar M. Reddy (ISQED, 2003)

Statistical Diagnosis for Intermittent Scan Chain Hold-Time Fault. - Yu Huang 005; Wu-Tung Cheng; Sudhakar M. Reddy; Cheng-Ju Hsieh; Yu-Ting Hung (ITC, 2003)

On-chip Compression of Output Responses with Unknown Values Using LFSR Reseeding. - Masao Naruse; Irith Pomeranz; Sudhakar M. Reddy; Sandip Kundu (ITC, 2003)

Convolutional Compaction of Test Responses. - Janusz Rajski; Jerzy Tyszer; Chen Wang 014; Sudhakar M. Reddy (ITC, 2003)

On Reducing Test Data Volume and Test Application Time for Multiple Scan Chain Designs. - Huaxing Tang; Sudhakar M. Reddy; Irith Pomeranz (ITC, 2003)

Optimizing SOC Test Resources Using Dual Sequences. - Wei Zou; Chris C. N. Chu; Sudhakar M. Reddy; Irith Pomeranz (VLSI-SoC (Selected Papers), 2003)

Static Test Compaction for Full-Scan Circuits Based on Combinational Test Sets and Non-Scan Sequential Test Sequences. - Irith Pomeranz; Sudhakar M. Reddy (VLSI Design, 2003)

GALLOP: Genetic Algorithm based Low Power FSM Synthesis by Simultaneous Partitioning and State Assignment. - Ganesh Venkataraman; Sudhakar M. Reddy; Irith Pomeranz (VLSI Design, 2003)

Application of Saluja-Karpovsky Compactors to Test Responses with Many Unknowns. - Janak H. Patel; Steven S. Lumetta; Sudhakar M. Reddy (VTS, 2003)

A Test Interface for Built-In Test of Non-Isolated Scanned Cores. - Irith Pomeranz; Sudhakar M. Reddy; Yervant Zorian (VTS, 2003)

SOC Test Scheduling Using Simulated Annealing. - Wei Zou; Sudhakar M. Reddy; Irith Pomeranz; Yu Huang 005 (VTS, 2003)

A Low Power Pseudo-Random BIST Technique. - Nadir Z. Basturkmen; Sudhakar M. Reddy; Irith Pomeranz (J. Electron. Test., 2003)

On Selecting Testable Paths in Scan Designs. - Yun Shao 002; Sudhakar M. Reddy; Irith Pomeranz; Seiji Kajihara (J. Electron. Test., 2003)

Reverse-order-restoration-based static test compaction for synchronous sequential circuits. - Ruifeng Guo; Sudhakar M. Reddy; Irith Pomeranz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

PROPTEST: a property-based test generator for synchronous sequential circuits. - Ruifeng Guo; Sudhakar M. Reddy; Irith Pomeranz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Test enrichment for path delay faults using multiple sets of target faults. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Theorems for identifying undetectable faults in partial-scan circuits. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Test data compression based on input-output dependence. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Transparent scan: a new approach to test generation and test compaction for scan circuits that incorporates limited scan operations. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

On test data volume reduction for multiple scan chain designs. - Sudhakar M. Reddy; Kohei Miyase; Seiji Kajihara; Irith Pomeranz (ACM Trans. Design Autom. Electr. Syst., 2003)

Multiple Scan Tree Design with Test Vector Modification. - Kohei Miyase; Seiji Kajihara; Sudhakar M. Reddy (Asian Test Symposium, 2004)

Properties of Maximally Dominating Faults. - Irith Pomeranz; Sudhakar M. Reddy (Asian Test Symposium, 2004)

A Postprocessing Procedure of Test Enrichment for Path Delay Faults. - Irith Pomeranz; Sudhakar M. Reddy (Asian Test Symposium, 2004)

Weighted Pseudo-Random BIST for N-Detection of Single Stuck-at Faults. - Chaowen Yu; Sudhakar M. Reddy; Irith Pomeranz (Asian Test Symposium, 2004)

On test generation for transition faults with minimized peak power dissipation. - Wei Li 023; Sudhakar M. Reddy; Irith Pomeranz (DAC, 2004)

Level of Similarity: A Metric for Fault Collapsing. - Irith Pomeranz; Sudhakar M. Reddy (DATE, 2004)

Z-Sets and Z-Detections: Circuit Characteristics that Simplify Fault Diagnosis. - Irith Pomeranz; Srikanth Venkataraman; Sudhakar M. Reddy; Bharath Seshadri (DATE, 2004)

Reducing Fault Latency in Concurrent On-Line Testing by Using Checking Functions over Internal Lines. - Irith Pomeranz; Sudhakar M. Reddy (DFT, 2004)

Concurrent On-Line Testing of Identical Circuits Through Output Comparison Using Non-Identical Input Vectors. - Irith Pomeranz; Sudhakar M. Reddy (DFT, 2004)

Enhanced 3-valued logic/fault simulation for full scan circuits using implicit logic values. - Seiji Kajihara; Kewal K. Saluja; Sudhakar M. Reddy (ETS, 2004)

On Undetectable Faults in Partial Scan Circuits Using Transparent-Scan. - Irith Pomeranz; Sudhakar M. Reddy (ICCD, 2004)

Test Application Time Reduction for Scan Circuits Using Limited Scan Operations. - Yonsang Cho; Irith Pomeranz; Sudhakar M. Reddy (ISQED, 2004)

Scan BIST Targeting Transition Faults Using a Markov Source. - Hangkyu Lee; Irith Pomeranz; Sudhakar M. Reddy (ISQED, 2004)

Z-DFD: Design-for-Diagnosability Based on the Concept of Z-Detection. - Irith Pomeranz; Srikanth Venkataraman; Sudhakar M. Reddy (ITC, 2004)

At-Speed Built-in Self-Repair Analyzer for Embedded Word-Oriented Memories. - Xiaogang Du; Sudhakar M. Reddy; Wu-Tung Cheng; Joseph Rayhawk; Nilanjan Mukherjee 001 (VLSI Design, 2004)

On Interconnecting Circuits with Multiple Scan Chains for Improved Test Data Compression. - Irith Pomeranz; Sudhakar M. Reddy (VLSI Design, 2004)

Defect Diagnosis Based on Pattern-Dependent Stuck-At Faults. - Irith Pomeranz; Srikanth Venkataraman; Sudhakar M. Reddy; M. Enamul Amyeen (VLSI Design, 2004)

Memory BIST Using ESP. - Xiaogang Du; Sudhakar M. Reddy; Don E. Ross; Wu-Tung Cheng; Joseph Rayhawk (VTS, 2004)

Don't Care Identification and Statistical Encoding for Test Data Compression. - Seiji Kajihara; Kenjiro Taniguchi; Kohei Miyase; Irith Pomeranz; Sudhakar M. Reddy (IEICE Trans. Inf. Syst., 2004)

Masking of Unknown Output Values during Output Response Compression byUsing Comparison Units. - Irith Pomeranz; Sandip Kundu; Sudhakar M. Reddy (IEEE Trans. Computers, 2004)

On Maximizing the Fault Coverage for a Given Test Length Limit in a Synchronous Sequential Circuit. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Computers, 2004)

A Measure of Quality for n-Detection Test Sets. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Computers, 2004)

Static Test Compaction for Full-Scan Circuits Based on Combinational Test Sets and Nonscan Input Sequences and a Lower Bound on the Number of Tests. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Computers, 2004)

Vector-restoration-based static compaction using random initial omission. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

On the characterization and efficient computation of hard-to-detect bridging faults. - Irith Pomeranz; Sudhakar M. Reddy; Sandip Kundu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Improving the stuck-at fault coverage of functional test sequences by using limited-scan operations. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Very Large Scale Integr. Syst., 2004)

Improved Delay Fault Coverage Using Subsets of Flip-flops to Launch Transitions. - Narendra Devta-Prasanna; Sudhakar M. Reddy; Arun Gunda; P. Krishnamurthy; Irith Pomeranz (Asian Test Symposium, 2005)

On Improving Defect Coverage of Stuck-at Fault Tests. - Kohei Miyase; Kenta Terashima; Seiji Kajihara; Xiaoqing Wen; Sudhakar M. Reddy (Asian Test Symposium, 2005)

Circuit Independent Weighted Pseudo-Random BIST Pattern Generator. - Chaowen Yu; Sudhakar M. Reddy; Irith Pomeranz (Asian Test Symposium, 2005)

Bridge Defect Diagnosis with Physical Information. - Wei Zou; Wu-Tung Cheng; Sudhakar M. Reddy (Asian Test Symposium, 2005)

Worst-Case and Average-Case Analysis of n-Detection Test Sets. - Irith Pomeranz; Sudhakar M. Reddy (DATE, 2005)

The Accidental Detection Index as a Fault Ordering Heuristic for Full-Scan Circuits. - Irith Pomeranz; Sudhakar M. Reddy (DATE, 2005)

Defect Aware Test Patterns. - Huaxing Tang; Gang Chen 011; Sudhakar M. Reddy; Chen Wang 014; Janusz Rajski; Irith Pomeranz (DATE, 2005)

Recovery During Concurrent On-Line Testing of Identical Circuits. - Irith Pomeranz; Sudhakar M. Reddy (DFT, 2005)

On Generating Pseudo-Functional Delay Fault Tests for Scan Designs. - Zhuo Zhang 008; Sudhakar M. Reddy; Irith Pomeranz (DFT, 2005)

A unified fault model and test generation procedure for interconnect opens and bridges. - Gang Chen 011; Sudhakar M. Reddy; Irith Pomeranz; Janusz Rajski; Piet Engelke; Bernd Becker 001 (ETS, 2005)

Using dummy bridging faults to define a reduced set of target faults. - Irith Pomeranz; Sudhakar M. Reddy (ETS, 2005)

Path-oriented transition fault test generation considering operating conditions. - Bharath Seshadri; Irith Pomeranz; Sudhakar M. Reddy; Sandip Kundu (ETS, 2005)

A Novel Method of Improving Transition Delay Fault Coverage Using Multiple Scan Enable Signals. - Narendra Devta-Prasanna; Arun Gunda; P. Krishnamurthy; Sudhakar M. Reddy; Irith Pomeranz (ICCD, 2005)

Battery-aware dynamic voltage scaling in multiprocessor embedded system. - Yuan Cai; Sudhakar M. Reddy; Irith Pomeranz; Bashir M. Al-Hashimi (ISCAS (1), 2005)

Dynamic Test Compaction for Bridging Faults. - Irith Pomeranz; Sudhakar M. Reddy (ISQED, 2005)

On Reducing Peak Current and Power during Test. - Wei Li 023; Sudhakar M. Reddy; Irith Pomeranz (ISVLSI, 2005)

Fault Diagnosis and Fault Model Aliasing. - Irith Pomeranz; Srikanth Venkataraman; Sudhakar M. Reddy (ISVLSI, 2005)

Methods for improving transition delay fault coverage using broadside tests. - Narendra Devta-Prasanna; Arun Gunda; P. Krishnamurthy; Sudhakar M. Reddy; Irith Pomeranz (ITC, 2005)

Full-speed field-programmable memory BIST architecture. - Xiaogang Du; Nilanjan Mukherjee 001; Wu-Tung Cheng; Sudhakar M. Reddy (ITC, 2005)

Forming N-detection test sets from one-detection test sets without test generation. - Irith Pomeranz; Sudhakar M. Reddy (ITC, 2005)

Full-speed field programmable memory BIST supporting multi-level looping. - Xiaogang Du; Nilanjan Mukherjee 001; Wu-Tung Cheng; Sudhakar M. Reddy (MTDT, 2005)

Distance Restricted Scan Chain Reordering to Enhance Delay Fault Coverage. - Wei Li 023; Seongmoon Wang; Srimat T. Chakradhar; Sudhakar M. Reddy (VLSI Design, 2005)

Tuple Detection for Path Delay Faults: A Method for Improving Test Set Quality. - Irith Pomeranz; Sudhakar M. Reddy (VLSI Design, 2005)

On Efficient X-Handling Using a Selective Compaction Scheme to Achieve High Test Response Compaction Ratios. - Huaxing Tang; Chen Wang 014; Janusz Rajski; Sudhakar M. Reddy; Jerzy Tyszer; Irith Pomeranz (VLSI Design, 2005)

On reducing test application time for scan circuits using limited scan operations and transfer sequences. - Yonsang Cho; Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

On masking of redundant faults in synchronous sequential circuits with design-for-testability logic. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

On fault equivalence, fault dominance, and incompletely specified test sets. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Finite memory test response compactors for embedded test applications. - Janusz Rajski; Jerzy Tyszer; Chen Wang 014; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Concurrent Online Testing of Identical Circuits Using Nonidentical Input Vectors. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Dependable Secur. Comput., 2005)

Autoscan: a scan design without external scan inputs or outputs. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Very Large Scale Integr. Syst., 2005)

Cache size selection for performance, energy and reliability of time-constrained systems. - Yuan Cai; Marcus T. Schmitz; Alireza Ejlali; Bashir M. Al-Hashimi; Sudhakar M. Reddy (ASP-DAC, 2006)

A Field Programmable Memory BIST Architecture Supporting Algorithms with Multiple Nested Loops. - Xiaogang Du; Nilanjan Mukherjee 001; Chris Hill; Wu-Tung Cheng; Sudhakar M. Reddy (ATS, 2006)

On the Replacement of Scan Chain Inputs by Primary Input Vectors. - Irith Pomeranz; Sudhakar M. Reddy (ATS, 2006)

Interconnect Open Defect Diagnosis with Physical Information. - Wei Zou; Wu-Tung Cheng; Sudhakar M. Reddy (ATS, 2006)

A test pattern ordering algorithm for diagnosis with truncated fail data. - Gang Chen 011; Sudhakar M. Reddy; Irith Pomeranz; Janusz Rajski (DAC, 2006)

Test compaction for transition faults under transparent-scan. - Irith Pomeranz; Sudhakar M. Reddy (DATE, 2006)

Test Generation for Open Defects in CMOS Circuits. - Narendra Devta-Prasanna; Arun Gunda; P. Krishnamurthy; Sudhakar M. Reddy; Irith Pomeranz (DFT, 2006)

Scan-Based Delay Fault Tests for Diagnosis of Transition Faults. - Irith Pomeranz; Sudhakar M. Reddy (DFT, 2006)

A Unified Method to Detect Transistor Stuck-Open Faults and Transition Delay Faults. - Narendra Devta-Prasanna; Arun Gunda; P. Krishnamurthy; Sudhakar M. Reddy; Irith Pomeranz (ETS, 2006)

Fault Collapsing for Transition Faults Using Extended Transition Faults. - Irith Pomeranz; Sudhakar M. Reddy (ETS, 2006)

A delay fault model for at-speed fault simulation and test generation. - Irith Pomeranz; Sudhakar M. Reddy (ICCAD, 2006)

A Partitioning Technique for Identification of Error-Capturing Scan Cells in Scan-BIST. - Chaowen Yu; Sudhakar M. Reddy; Irith Pomeranz (IOLTS, 2006)

Fault Detection by Output Response Comparison of Identical Circuits Using Half-Frequency Compatible Sequences. - Irith Pomeranz; Sudhakar M. Reddy (ITC, 2006)

Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs. - Santiago Remersaro; Xijiang Lin; Zhuo Zhang 008; Sudhakar M. Reddy; Irith Pomeranz; Janusz Rajski (ITC, 2006)

New Procedures to Identify Redundant Stuck-At Faults and Removal of Redundant Logic. - Gang Chen 011; Sudhakar M. Reddy; Irith Pomeranz; Janusz Rajski (VLSI Design, 2006)

The Cut Delay Fault Model for Guiding the Generation of n-Detection Test Sets for Transition Faults. - Irith Pomeranz; Sudhakar M. Reddy (VLSI Design, 2006)

On Methods to Improve Location Based Logic Diagnosis. - Wei Zou; Wu-Tung Cheng; Sudhakar M. Reddy; Huaxing Tang (VLSI Design, 2006)

A Test Generation Procedure for Avoiding the Detection of Functionally Redundant Transition Faults. - Hangkyu Lee; Irith Pomeranz; Sudhakar M. Reddy (VTS, 2006)

Dominance Based Analysis for Large Volume Production Fail Diagnosis. - Bharath Seshadri; Irith Pomeranz; Srikanth Venkataraman; M. Enamul Amyeen; Sudhakar M. Reddy (VTS, 2006)

Scan Tests with Multiple Fault Activation Cycles for Delay Faults. - Zhuo Zhang 008; Sudhakar M. Reddy; Irith Pomeranz; Xijiang Lin; Janusz Rajski (VTS, 2006)

On the Use of Functional Test Generation in Diagnostic Test Generation for Synchronous Sequential Circuits. - Irith Pomeranz; Sudhakar M. Reddy (V&D@FLoC, 2006)

On Generating Tests that Avoid the Detection of Redundant Faults in Synchronous Sequential Circuits with Full Scan. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Computers, 2006)

Scan-BIST based on transition probabilities for circuits with single and multiple scan chains. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Transparent DFT: a design for testability and test generation approach for synchronous sequential circuits. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Generation of Functional Broadside Tests for Transition Faults. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Using Dummy Bridging Faults to Define Reduced Sets of Target Faults. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Improved n-Detection Test Sequences Under Transparent Scan. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Warning: Launch off Shift Tests for Delay Faults May Contribute to Test Escapes. - Zhuo Zhang 008; Sudhakar M. Reddy; Irith Pomeranz (ASP-DAC, 2007)

Diagnostic Test Generation Targeting Equivalence Classes. - Irith Pomeranz; Sudhakar M. Reddy (ATS, 2007)

Enhanced Broadside Testing for Improved Transition Fault Coverage. - Irith Pomeranz; Sudhakar M. Reddy (ATS, 2007)

On test generation by input cube avoidance. - Irith Pomeranz; Sudhakar M. Reddy (DATE, 2007)

A-Diagnosis: A Complement to Z-Diagnosis. - Irith Pomeranz; Sudhakar M. Reddy (DFT, 2007)

Semi-Concurrent On-Line Testing of Transition Faults Through Output Response Comparison of Identical Circuits. - Irith Pomeranz; Sudhakar M. Reddy (DFT, 2007)

Diagnostic Test Generation Based on Subsets of Faults. - Irith Pomeranz; Sudhakar M. Reddy (ETS, 2007)

Reducing the Energy Consumption in Fault-Tolerant Distributed Embedded Systems with Time-Constraint. - Yuan Cai; Sudhakar M. Reddy; Bashir M. Al-Hashimi (ISQED, 2007)

Interconnect open defect diagnosis with minimal physical information. - Chen Liu; Wei Zou; Sudhakar M. Reddy; Wu-Tung Cheng; Manish Sharma; Huaxing Tang (ITC, 2007)

On the saturation of n-detection test sets with increased n. - Irith Pomeranz; Sudhakar M. Reddy (ITC, 2007)

Faster defect localization in nanometer technology based on defective cell diagnosis. - Manish Sharma; Wu-Tung Cheng; Ting-Pu Tai; Y. S. Cheng; Will Hsu; Chen Liu; Sudhakar M. Reddy; Albert Mann (ITC, 2007)

Equivalence and Dominance Relations Between Fault Pairs and Their Use in Fault Pair Collapsing for Fault Diagnosis. - Irith Pomeranz; Sudhakar M. Reddy (VLSI Design, 2007)

Functional Broadside Tests with Different Levels of Reachability. - Irith Pomeranz; Sudhakar M. Reddy (VLSI Design, 2007)

Low Shift and Capture Power Scan Tests. - Santiago Remersaro; Xijiang Lin; Sudhakar M. Reddy; Irith Pomeranz; Janusz Rajski (VLSI Design, 2007)

Autoscan-Invert: An Improved Scan Design without External Scan Inputs or Outputs. - Irith Pomeranz; Sudhakar M. Reddy (VTS, 2007)

Speeding Up Effect-Cause Defect Diagnosis Using a Small Dictionary. - Wei Zou; Wu-Tung Cheng; Sudhakar M. Reddy; Huaxing Tang (VTS, 2007)

Scan-Based Tests with Low Switching Activity. - Santiago Remersaro; Xijiang Lin; Sudhakar M. Reddy; Irith Pomeranz; Janusz Rajski (IEEE Des. Test Comput., 2007)

Worst-case and average-case analysis of n-detection test sets and test generation strategies. - Irith Pomeranz; Sudhakar M. Reddy (IET Comput. Digit. Tech., 2007)

Effectiveness of scan-based delay fault tests in diagnosis of transition faults. - Irith Pomeranz; Sudhakar M. Reddy (IET Comput. Digit. Tech., 2007)

Enhancing delay fault coverage through low-power segmented scan. - Zhuo Zhang 008; Sudhakar M. Reddy; Irith Pomeranz; Janusz Rajski; Bashir M. Al-Hashimi (IET Comput. Digit. Tech., 2007)

Generation of Broadside Transition-Fault Test Sets That Detect Four-Way Bridging Faults. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

z-Diagnosis: A Framework for Diagnostic Fault Simulation and Test Generation Utilizing Subsets of Outputs. - Irith Pomeranz; Sudhakar M. Reddy; Srikanth Venkataraman (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Workload-ahead-driven online energy minimization techniques for battery-powered embedded systems with time-constraints. - Yuan Cai; Marcus T. Schmitz; Bashir M. Al-Hashimi; Sudhakar M. Reddy (ACM Trans. Design Autom. Electr. Syst., 2007)

Forming N-detection test sets without test generation. - Irith Pomeranz; Sudhakar M. Reddy (ACM Trans. Design Autom. Electr. Syst., 2007)

Circuit lines for guiding the generation of random test sequences for synchronous sequential circuits. - Irith Pomeranz; Sudhakar M. Reddy (ASP-DAC, 2008)

Test vector chains for increased targeted and untargeted fault coverage. - Irith Pomeranz; Sudhakar M. Reddy (ASP-DAC, 2008)

Hyperactive Faults Dictionary to Increase Diagnosis Throughput. - Chen Liu; Wu-Tung Cheng; Huaxing Tang; Sudhakar M. Reddy; Wei Zou; Manish Sharma (ATS, 2008)

On tests to detect via opens in digital CMOS circuits. - Sudhakar M. Reddy; Irith Pomeranz; Chen Liu (DAC, 2008)

A Bridging Fault Model Where Undetectable Faults Imply Logic Redundancy. - Irith Pomeranz; Sudhakar M. Reddy (DATE, 2008)

On Reducing Circuit Malfunctions Caused by Soft Errors. - Ilia Polian; Sudhakar M. Reddy; Irith Pomeranz; Xun Tang; Bernd Becker 001 (DFT, 2008)

ATPG Heuristics Dependant Observation Point Insertion for Enhanced Compaction and Data Volume Reduction. - Santiago Remersaro; Janusz Rajski; Thomas Rinderknecht; Sudhakar M. Reddy; Irith Pomeranz (DFT, 2008)

Detection of Transistor Stuck-Open Faults in Asynchronous Inputs of Scan Cells. - Fan Yang 060; Sreejit Chakravarty; Narendra Devta-Prasanna; Sudhakar M. Reddy; Irith Pomeranz (DFT, 2008)

Bridge Defect Diagnosis for Multiple-Voltage Design. - S. Saqib Khursheed; Paul M. Rosinger; Bashir M. Al-Hashimi; Sudhakar M. Reddy; Peter Harrod (ETS, 2008)

Safe Fault Collapsing Based on Dominance Relations. - Irith Pomeranz; Sudhakar M. Reddy (ETS, 2008)

An Enhanced Logic BIST Architecture for Online Testing. - Fan Yang 060; Sreejit Chakravarty; Narendra Devta-Prasanna; Sudhakar M. Reddy; Irith Pomeranz (IOLTS, 2008)

Scalable Calculation of Logical Masking Effects for Selective Hardening Against Soft Errors. - Ilia Polian; Sudhakar M. Reddy; Bernd Becker 001 (ISVLSI, 2008)

Detection of Internal Stuck-open Faults in Scan Chains. - Fan Yang 060; Sreejit Chakravarty; Narendra Devta-Prasanna; Sudhakar M. Reddy; Irith Pomeranz (ITC, 2008)

Design-for-Testability for Improved Path Delay Fault Coverage of Critical Paths. - Irith Pomeranz; Sudhakar M. Reddy (VLSI Design, 2008)

Design-for-Testability for Synchronous Sequential Circuits that Maintains Functional Switching Activity. - Irith Pomeranz; Sudhakar M. Reddy (VLSI Design, 2008)

On Common-Mode Skewed-Load and Broadside Tests. - Irith Pomeranz; Sudhakar M. Reddy; Sandip Kundu (VLSI Design, 2008)

Synthesis for Broadside Testability of Transition Faults. - Irith Pomeranz; Sudhakar M. Reddy (VTS, 2008)

Expanded Definition of Functional Operation Conditions and its Effects on the Computation of Functional Broadside Tests. - Irith Pomeranz; Sudhakar M. Reddy (VTS, 2008)

On the Detectability of Scan Chain Internal Faults - An Industrial Case Study. - Fan Yang 060; Sreejit Chakravarty; Narendra Devta-Prasanna; Sudhakar M. Reddy; Irith Pomeranz (VTS, 2008)

On Detection of Bridge Defects with Stuck-at Tests. - Kohei Miyase; Kenta Terashima; Xiaoqing Wen; Seiji Kajihara; Sudhakar M. Reddy (IEICE Trans. Inf. Syst., 2008)

Functional Broadside Tests with Minimum and Maximum Switching Activity. - Irith Pomeranz; Sudhakar M. Reddy (J. Low Power Electron., 2008)

On Complete Functional Broadside Tests for Transition Faults. - Hangkyu Lee; Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Unspecified Transition Faults: A Transition Fault Model for At-Speed Fault Simulation and Test Generation. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Primary Input Vectors to Avoid in Random Test Sequences for Synchronous Sequential Circuits. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Scan-Based Delay Test Types and Their Effect on Power Dissipation During Test. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

On the Saturation of n-Detection Test Generation by Different Definitions With Increased n. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Transition Path Delay Faults: A New Path Delay Fault Model for Small and Large Delay Defects. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Improving the Transition Fault Coverage of Functional Broadside Tests by Observation Point Insertion. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Dynamic test compaction for a random test generation procedure with input cube avoidance. - Irith Pomeranz; Sudhakar M. Reddy (ASP-DAC, 2009)

Detectability of internal bridging faults in scan chains. - Fan Yang 060; Sreejit Chakravarty; Narendra Devta-Prasanna; Sudhakar M. Reddy; Irith Pomeranz (ASP-DAC, 2009)

N-distinguishing Tests for Enhanced Defect Diagnosis. - Gang Chen 011; Janusz Rajski; Sudhakar M. Reddy; Irith Pomeranz (Asian Test Symposium, 2009)

Dynamic Compaction in SAT-Based ATPG. - Alejandro Czutro; Ilia Polian; Piet Engelke; Sudhakar M. Reddy; Bernd Becker 001 (Asian Test Symposium, 2009)

Fault Diagnosis under Transparent-Scan. - Irith Pomeranz; Sudhakar M. Reddy (Asian Test Symposium, 2009)

On Improving Diagnostic Test Generation for Scan Chain Failures. - Xun Tang; Ruifeng Guo; Wu-Tung Cheng; Sudhakar M. Reddy; Yu Huang 005 (Asian Test Symposium, 2009)

A scalable method for the generation of small test sets. - Santiago Remersaro; Janusz Rajski; Sudhakar M. Reddy; Irith Pomeranz (DATE, 2009)

Improving compressed test pattern generation for multiple scan chain failure diagnosis. - Xun Tang; Ruifeng Guo; Wu-Tung Cheng; Sudhakar M. Reddy (DATE, 2009)

On-chip Generation of the Second Primary Input Vectors of Broadside Tests. - Irith Pomeranz; Sudhakar M. Reddy (DFT, 2009)

Hazard-Based Detection Conditions for Improved Transition Fault Coverage of Functional Test Sequences. - Irith Pomeranz; Sudhakar M. Reddy (DFT, 2009)

Improving the Detectability of Resistive Open Faults in Scan Cells. - Fan Yang 060; Sreejit Chakravarty; Narendra Devta-Prasanna; Sudhakar M. Reddy; Irith Pomeranz (DFT, 2009)

Input Cubes with Lingering Synchronization Effects and their Use in Random Sequential Test Generation. - Irith Pomeranz; Sudhakar M. Reddy (ETS, 2009)

Partitioned n-detection test generation. - Irith Pomeranz; Sudhakar M. Reddy (ACM Great Lakes Symposium on VLSI, 2009)

Definition and application of approximate necessary assignments. - Irith Pomeranz; Sudhakar M. Reddy (ACM Great Lakes Symposium on VLSI, 2009)

State persistence: a property for guiding test generation. - Irith Pomeranz; Sudhakar M. Reddy (ACM Great Lakes Symposium on VLSI, 2009)

Markov source based test length optimized SCAN-BIST architecture. - Aftab Farooqi; Richard O. Gale; Sudhakar M. Reddy; Brian Nutter; Chris Monico (ISQED, 2009)

TIGUAN: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis. - Alejandro Czutro; Ilia Polian; Matthew Lewis 004; Piet Engelke; Sudhakar M. Reddy; Bernd Becker 001 (VLSI Design, 2009)

The Effect of Filling the Unspecified Values of a Test Set on the Test Set Quality. - Irith Pomeranz; Sudhakar M. Reddy (VLSI Design, 2009)

Definition and generation of partially-functional broadside tests. - Irith Pomeranz; Sudhakar M. Reddy (IET Comput. Digit. Tech., 2009)

Same/different fault dictionary: an extended pass/fail fault dictionary with improved diagnostic resolution. - Irith Pomeranz; Sudhakar M. Reddy (IET Comput. Digit. Tech., 2009)

Test vector chains for increasing the fault coverage and numbers of detections. - Irith Pomeranz; Sudhakar M. Reddy (IET Comput. Digit. Tech., 2009)

Test compaction methods for transition faults under transparent-scan. - Irith Pomeranz; Sudhakar M. Reddy (IET Comput. Digit. Tech., 2009)

Process Variation-Aware Test for Resistive Bridges. - Urban Ingelsson; Bashir M. Al-Hashimi; S. Saqib Khursheed; Sudhakar M. Reddy; Peter Harrod (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Diagnosis of Multiple-Voltage Design With Bridge Defect. - S. Saqib Khursheed; Bashir M. Al-Hashimi; Sudhakar M. Reddy; Peter Harrod (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Functional Broadside Tests Under an Expanded Definition of Functional Operation Conditions. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Double-Single Stuck-at Faults: A Delay Fault Model for Synchronous Sequential Circuits. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Forward-Looking Reverse Order Fault Simulation for n -Detection Test Sets. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Semiconcurrent Online Testing of Transition Faults through Output Response Comparison of Identical Circuits. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Dependable Secur. Comput., 2009)

Using stuck-at tests to form scan-based tests for transition faults in standard-scan circuits. - Irith Pomeranz; Sudhakar M. Reddy (ACM Trans. Design Autom. Electr. Syst., 2009)

Random Test Generation With Input Cube Avoidance. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Functional and partially-functional skewed-load tests. - Irith Pomeranz; Sudhakar M. Reddy (ASP-DAC, 2010)

On Bias in Transition Coverage of Test Sets for Path Delay Faults. - Irith Pomeranz; Sudhakar M. Reddy (Asian Test Symposium, 2010)

Diagnosis of Multiple Physical Defects Using Logic Fault Models. - Xun Tang; Wu-Tung Cheng; Ruifeng Guo; Sudhakar M. Reddy (Asian Test Symposium, 2010)

Reducing the storage requirements of a test sequence by using a background vector. - Irith Pomeranz; Sudhakar M. Reddy (DATE, 2010)

On reset based functional broadside tests. - Irith Pomeranz; Sudhakar M. Reddy (DATE, 2010)

Gradual Diagnostic Test Generation Based on the Structural Distance between Indistinguished Fault Pairs. - Irith Pomeranz; Sudhakar M. Reddy (DFT, 2010)

Input test data volume reduction based on test vector chains. - Irith Pomeranz; Sudhakar M. Reddy (ETS, 2010)

Deterministic broadside test generation for transition path delay faults. - Bo Yao 002; Irith Pomeranz; Sudhakar M. Reddy (ACM Great Lakes Symposium on VLSI, 2010)

Selecting state variables for improved on-line testability through output response comparison of identical circuits. - Irith Pomeranz; Sudhakar M. Reddy (IOLTS, 2010)

Multiple fault activation cycle tests for transistor stuck-open faults. - Narendra Devta-Prasanna; Arun Gunda; Sudhakar M. Reddy; Irith Pomeranz (ITC, 2010)

Low capture power at-speed test in EDT environment. - Elham K. Moghaddam; Janusz Rajski; Sudhakar M. Reddy; Xijiang Lin; Nilanjan Mukherjee 001; Mark Kassab (ITC, 2010)

Output-Dependent Diagnostic Test Generation. - Irith Pomeranz; Sudhakar M. Reddy (VLSI Design, 2010)

Identifying Tests for Logic Fault Models Involving Subsets of Lines without Fault Enumeration. - Irith Pomeranz; Sudhakar M. Reddy (VLSI Design, 2010)

At-speed scan test with low switching activity. - Elham K. Moghaddam; Janusz Rajski; Sudhakar M. Reddy; Mark Kassab (VTS, 2010)

Forming multi-cycle tests for delay faults by concatenating broadside tests. - Irith Pomeranz; Sudhakar M. Reddy (VTS, 2010)

On multiple bridging faults. - Irith Pomeranz; Sudhakar M. Reddy (VTS, 2010)

Diagnosis of path delay faults based on low-coverage tests. - Irith Pomeranz; Sudhakar M. Reddy (IET Comput. Digit. Tech., 2010)

Static test compaction for diagnostic test sets of full-scan circuits. - Irith Pomeranz; Sudhakar M. Reddy (IET Comput. Digit. Tech., 2010)

Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability Analysis. - Alejandro Czutro; Ilia Polian; Matthew Lewis 004; Piet Engelke; Sudhakar M. Reddy; Bernd Becker 001 (Int. J. Parallel Program., 2010)

Test Sequences with Reduced and Increased Switching Activity. - Irith Pomeranz; Sudhakar M. Reddy (J. Low Power Electron., 2010)

Equivalence, Dominance, and Similarity Relations between Fault Pairs and a Fault Pair Collapsing Process for Fault Diagnosis. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Computers, 2010)

TOV: Sequential Test Generation by Ordering of Test Vectors. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

On Test Generation With Test Vector Improvement. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

On Clustering of Undetectable Single Stuck-At Faults and Test Quality in Full-Scan Circuits. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Hazard-Based Detection Conditions for Improved Transition Path Delay Fault Coverage. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

On Undetectable Faults and Fault Diagnosis. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Hazard-Based Detection Conditions for Improved Transition Fault Coverage of Scan-Based Tests. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Path Selection for Transition Path Delay Faults. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Robust Fault Models Where Undetectable Faults Imply Logic Redundancy. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Switching Activity as a Test Compaction Heuristic for Transition Faults. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Selection of a Fault Model for Fault Diagnosis Based on Unique Responses. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Fault diagnosis aware ATE assisted test response compaction. - J. M. Howard; Sudhakar M. Reddy; Irith Pomeranz; Bernd Becker 001 (ASP-DAC, 2011)

On Using Design Partitioning to Reduce Diagnosis Memory Footprint. - Xiaoxin Fan; Huaxing Tang; Sudhakar M. Reddy; Wu-Tung Cheng; Brady Benware (Asian Test Symposium, 2011)

Low Test Data Volume Low Power At-Speed Delay Tests Using Clock-Gating. - Elham K. Moghaddam; Janusz Rajski; Sudhakar M. Reddy; Jakub Janicki (Asian Test Symposium, 2011)

Analysis of Resistive Bridge Defect Delay Behavior in the Presence of Process Variation. - Shida Zhong; S. Saqib Khursheed; Bashir M. Al-Hashimi; Sudhakar M. Reddy; Krishnendu Chakrabarty (Asian Test Symposium, 2011)

Hyper-graph based partitioning to reduce DFT cost for pre-bond 3D-IC testing. - Amit Kumar 004; Sudhakar M. Reddy; Irith Pomeranz; Bernd Becker 001 (DATE, 2011)

Max-Fill: A method to generate high quality delay tests. - Xiaoxin Fan; Sudhakar M. Reddy; Irith Pomeranz (DDECS, 2011)

Diagnosis of Multiple Faults Based on Fault-Tuple Equivalence Tree. - Xun Tang; Wu-Tung Cheng; Ruifeng Guo; Huaxing Tang; Sudhakar M. Reddy (DFT, 2011)

Genetic algorithm based approach for segmented testing. - Xiaoxin Fan; Sudhakar M. Reddy; Senling Wang; Seiji Kajihara; Yasuo Sato (DSN Workshops, 2011)

Low power compression utilizing clock-gating. - Janusz Rajski; Elham K. Moghaddam; Sudhakar M. Reddy (ITC, 2011)

Primary input cones based on test sequences in synchronous sequential circuits. - Irith Pomeranz; Sudhakar M. Reddy (IET Comput. Digit. Tech., 2011)

Two-dimensional partially functional broadside tests. - Irith Pomeranz; Sudhakar M. Reddy (IET Comput. Digit. Tech., 2011)

Sizes of test sets for path delay faults using strong and weak non-robust tests. - Irith Pomeranz; Sudhakar M. Reddy (IET Comput. Digit. Tech., 2011)

Ranking of input cubes based on their lingering synchronisation effects and their use in random sequential test generation. - Irith Pomeranz; Sudhakar M. Reddy (IET Comput. Digit. Tech., 2011)

Transparent-Segmented-Scan without the Routing Overhead of Segmented-Scan. - Irith Pomeranz; Sudhakar M. Reddy (J. Low Power Electron., 2011)

Modeling and Mitigating Transient Errors in Logic Circuits. - Ilia Polian; John P. Hayes; Sudhakar M. Reddy; Bernd Becker 001 (IEEE Trans. Dependable Secur. Comput., 2011)

Reducing the switching activity of test sequences under transparent-scan. - Irith Pomeranz; Sudhakar M. Reddy (ACM Trans. Design Autom. Electr. Syst., 2011)

Fixed-State Tests for Delay Faults in Scan Designs. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Input Necessary Assignments for Testing of Path Delay Faults in Standard-Scan Circuits. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Very Large Scale Integr. Syst., 2011)

On Functional Broadside Tests With Functional Propagation Conditions. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Broadside and Functional Broadside Tests for Partial-Scan Circuits. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Static Test Data Volume Reduction Using Complementation or Modulo- M Addition. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Reducing the Storage Requirements of a Test Sequence by Using One or Two Background Vectors. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Test Strength: A Quality Metric for Transition Fault Tests in Full-Scan Circuits. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Diagnosis of Cell Internal Defects with Multi-cycle Test Patterns. - Xiaoxin Fan; Manish Sharma; Wu-Tung Cheng; Sudhakar M. Reddy (Asian Test Symposium, 2012)

Session Summary III: Power-Aware Testing: Present and Future. - Xiaoqing Wen; Sudhakar M. Reddy (Asian Test Symposium, 2012)

Performance aware partitioning for 3D-SOCs. - Amit Kumar 004; Sudhakar M. Reddy; Bernd Becker 001; Irith Pomeranz (ISOCC, 2012)

TSV and DFT cost aware circuit partitioning for 3D-SOCs. - Amit Kumar 004; Sudhakar M. Reddy; Irith Pomeranz; Bernd Becker 001 (ISQED, 2012)

Improved volume diagnosis throughput using dynamic design partitioning. - Xiaoxin Fan; Huaxing Tang; Yu Huang 005; Wu-Tung Cheng; Sudhakar M. Reddy; Brady Benware (ITC, 2012)

Functional test of small-delay faults using SAT and Craig interpolation. - Matthias Sauer 002; Stefan Kupferschmid; Alexander Czutro; Ilia Polian; Sudhakar M. Reddy; Bernd Becker 001 (ITC, 2012)

Analysis of Reachable Sensitisable Paths in Sequential Circuits with SAT and Craig Interpolation. - Matthias Sauer 002; Stefan Kupferschmid; Alejandro Czutro; Sudhakar M. Reddy; Bernd Becker 001 (VLSI Design, 2012)

Reset and partial-reset-based functional broadside tests. - Irith Pomeranz; Sudhakar M. Reddy (IET Comput. Digit. Tech., 2012)

Resolution of Diagnosis Based on Transition Faults. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Very Large Scale Integr. Syst., 2012)

On the Generation of Compact Deterministic Test Sets for BIST Ready Designs. - Amit Kumar 004; Janusz Rajski; Sudhakar M. Reddy; Thomas Rinderknecht (Asian Test Symposium, 2013)

On the generation of compact test sets. - Amit Kumar 004; Janusz Rajski; Sudhakar M. Reddy; Chen Wang 014 (ITC, 2013)

Distributed dynamic partitioning based diagnosis of scan chain. - Yu Huang 005; Xiaoxin Fan; Huaxing Tang; Manish Sharma; Wu-Tung Cheng; Brady Benware; Sudhakar M. Reddy (VTS, 2013)

Fundamentals of Small-Delay Defect Testing. - Sudhakar M. Reddy; Peter Maxwell (Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits, 2014)

Circuit Parameter Independent Test Pattern Generation for Interconnect Open Defects. - Dominik Erb; Karsten Scheibler; Matthias Sauer 002; Sudhakar M. Reddy; Bernd Becker 001 (ATS, 2014)

Isometric test compression with low toggling activity. - Amit Kumar 004; Mark Kassab; Elham K. Moghaddam; Nilanjan Mukherjee 001; Janusz Rajski; Sudhakar M. Reddy; Jerzy Tyszer; Chen Wang 014 (ITC, 2014)

SAT-Based Test Pattern Generation with Improved Dynamic Compaction. - Alexander Czutro; Sudhakar M. Reddy; Ilia Polian; Bernd Becker 001 (VLSID, 2014)

A Cube-Aware Compaction Method for Scan ATPG. - Sharada Jha; Kameshwar Chandrasekar; Weixin Wu; Ramesh Sharma; Sanjay Sengupta; Sudhakar M. Reddy (VLSID, 2014)

Efficient SAT-Based Circuit Initialization for Larger Designs. - Matthias Sauer 002; Sven Reimer; Sudhakar M. Reddy; Bernd Becker 001 (VLSID, 2014)

On achieving minimal size test sets for scan designs. - Sudhakar M. Reddy; Zhuo Zhang 008 (it Inf. Technol., 2014)

On generating high quality tests based on cell functions. - Xijiang Lin; Sudhakar M. Reddy (ITC, 2015)

Embedded Tutorial ET2: Volume Diagnosis for Yield Improvement. - Wu-Tung Cheng; Sudhakar M. Reddy (VLSID, 2015)

Using Boolean Tests to Improve Detection of Transistor Stuck-Open Faults in CMOS Digital Logic Circuits. - Xijiang Lin; Sudhakar M. Reddy; Janusz Rajski (VLSID, 2015)

Multi-cycle Circuit Parameter Independent ATPG for interconnect open defects. - Dominik Erb; Karsten Scheibler; Matthias Sauer 002; Sudhakar M. Reddy; Bernd Becker 001 (VTS, 2015)

Improving diagnosis resolution of a fault detection test set. - Andreas Riefert; Matthias Sauer 002; Sudhakar M. Reddy; Bernd Becker 001 (VTS, 2015)

Isometric Test Data Compression. - Amit Kumar 004; Mark Kassab; Elham K. Moghaddam; Nilanjan Mukherjee 001; Janusz Rajski; Sudhakar M. Reddy; Jerzy Tyszer; Chen Wang 014 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

On Achieving Maximal Chain Diagnosis Resolution through Test Pattern Selection. - Xijiang Lin; Sudhakar M. Reddy; Wu-Tung Cheng (ATS, 2016)

On the Switching Activity in Faulty Circuits During Test Application. - Irith Pomeranz; Sudhakar M. Reddy (ATS, 2016)

Transistor stuck-on fault detection tests for digital CMOS circuits. - Xijiang Lin; Sudhakar M. Reddy; Janusz Rajski (ETS, 2016)

Minimal area test points for deterministic patterns. - Yingdi Liu; Elham K. Moghaddam; Nilanjan Mukherjee 001; Sudhakar M. Reddy; Janusz Rajski; Jerzy Tyszer (ITC, 2016)

Automatic Identification of Yield Limiting Layout Patterns Using Root Cause Deconvolution on Volume Scan Diagnosis Data. - Wu-Tung Cheng; Randy Klingenberg; Brady Benware; Wu Yang; Manish Sharma; Geir Eide; Yue Tian; Sudhakar M. Reddy; Yan Pan; Sherwin Fernandes; Atul Chittora (ATS, 2017)

Fast and waveform-accurate hazard-aware SAT-based TSOF ATPG. - Jan Burchard; Dominik Erb; Adit D. Singh; Sudhakar M. Reddy; Bernd Becker 001 (DATE, 2017)

Volume diagnosis data mining. - Wu-Tung Cheng; Yue Tian; Sudhakar M. Reddy (ETS, 2017)

Test generation for open and delay faults in CMOS circuits. - Cheng-Hung Wu; Kuen-Jong Lee; Sudhakar M. Reddy (ITC-Asia, 2017)

Accurate Diagnosis of Interconnect Open Defects Based on the Robust Enhanced Aggressor Victim Model. - Pascal Raiola; Dominik Erb; Sudhakar M. Reddy; Bernd Becker 001 (VLSID, 2017)

Efficient SAT-based generation of hazard-activated TSOF tests. - Jan Burchard; Dominik Erb; Sudhakar M. Reddy; Adit D. Singh; Bernd Becker 001 (VTS, 2017)

Embedded Deterministic Test Points. - Cesar Acero; Derek Feltham; Yingdi Liu; Elham K. Moghaddam; Nilanjan Mukherjee 001; Marek Patyra; Janusz Rajski; Sudhakar M. Reddy; Jerzy Tyszer; Justyna Zawada (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Recycled IC detection through aging sensor. - Daniele Rossi 001; Vasileios Tenentes; S. Saqib Khursheed; Sudhakar M. Reddy (ETS, 2018)

Generating Compact Test Patterns for Stuck-at Faults and Transition Faults in One ATPG Run. - Yi-Cheng Kung; Kuen-Jong Lee; Sudhakar M. Reddy (ITC-Asia, 2018)

Generating Compact Test Patterns for DC and AC Faults Using One ATPG Run. - Yi-Cheng Kung; Kuen-Jong Lee; Sudhakar M. Reddy (ITC, 2018)

Deterministic Stellar BIST for In-System Automotive Test. - Yingdi Liu; Nilanjan Mukherjee 001; Janusz Rajski; Sudhakar M. Reddy; Jerzy Tyszer (ITC, 2018)

Staggered ATPG with capture-per-cycle observation test points. - Yingdi Liu; Janusz Rajski; Sudhakar M. Reddy; Jedrzej Solecki; Jerzy Tyszer (VTS, 2018)

On the Generation of Waveform-Accurate Hazard and Charge-Sharing Aware Tests for Transistor Stuck-Off Faults in CMOS Logic Circuits. - Jan Burchard; Dominik Erb; Sudhakar M. Reddy; Adit D. Singh; Bernd Becker 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Exploiting Aging Benefits for the Design of Reliable Drowsy Cache Memories. - Daniele Rossi 001; Vasileios Tenentes; Sudhakar M. Reddy; Bashir M. Al-Hashimi; Andrew D. Brown (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

A Repair-for-Diagnosis Methodology for Logic Circuits. - Cheng-Hung Wu; Sheng-Lin Lin; Kuen-Jong Lee; Sudhakar M. Reddy (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Deep Learning Based Test Compression Analyzer. - Cheng-Hung Wu; Yu Huang 005; Kuen-Jong Lee; Wu-Tung Cheng; Gaurav Veda; Sudhakar M. Reddy; Chun-Cheng Hu; Chong-Siao Ye (ATS, 2019)

Resynthesis for Avoiding Undetectable Faults Based on Design-for-Manufacturability Guidelines. - Naixing Wang; Irith Pomeranz; Sudhakar M. Reddy; Arani Sinha; Srikanth Venkataraman (DATE, 2019)

On Generating Fault Diagnosis Patterns for Designs with X Sources. - Xijiang Lin; Sudhakar M. Reddy (ETS, 2019)

A supervised machine learning application in volume diagnosis. - Yue Tian; Gaurav Veda; Wu-Tung Cheng; Manish Sharma; Huaxing Tang; Neerja Bawaskar; Sudhakar M. Reddy (ETS, 2019)

Layout Resynthesis by Applying Design-for-manufacturability Guidelines to Avoid Low-coverage Areas of a Cell-based Design. - Naixing Wang; Irith Pomeranz; Sudhakar M. Reddy; Arani Sinha; Srikanth Venkataraman (ACM Trans. Design Autom. Electr. Syst., 2019)

An Efficient Diagnosis-Aware ATPG Procedure to Enhance Diagnosis Resolution and Test Compaction. - Cheng-Hung Wu; Kuen-Jong Lee; Sudhakar M. Reddy (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Efficient Prognostication of Pattern Count with Different Input Compression Ratios. - Fong-Jyun Tsai; Chong-Siao Ye; Yu Huang 005; Kuen-Jong Lee; Wu-Tung Cheng; Sudhakar M. Reddy; Mark Kassab; Janusz Rajski (ETS, 2020)

Estimation of Test Data Volume for Scan Architectures with Different Numbers of Input Channels. - Fong-Jyun Tsai; Chong-Siao Ye; Yu Huang 005; Kuen-Jong Lee; Wu-Tung Cheng; Sudhakar M. Reddy; Mark Kassab; Janusz Rajski; Shi-Xuan Zheng (ITC-Asia, 2020)

Prediction of Test Pattern Count and Test Data Volume for Scan Architectures under Different Input Channel Configurations. - Fong-Jyun Tsai; Chong-Siao Ye; Kuen-Jong Lee; Shi-Xuan Zheng; Yu Huang 005; Wu-Tung Cheng; Sudhakar M. Reddy; Mark Kassab; Janusz Rajski; Chen Wang 014; Justyna Zawada (ITC, 2020)

LFSR generation for high test coverage and low hardware overhead. - Leonel Hernández Martínez; S. Saqib Khursheed; Sudhakar M. Reddy (IET Comput. Digit. Tech., 2020)

Generating Single- and Double-Pattern Tests for Multiple CMOS Fault Models in One ATPG Run. - Yi-Cheng Kung; Kuen-Jong Lee; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Deterministic Stellar BIST for Automotive ICs. - Yingdi Liu; Nilanjan Mukherjee 001; Janusz Rajski; Sudhakar M. Reddy; Jerzy Tyszer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Accurate Estimation of Test Pattern Counts for a Wide-Range of EDT Input/Output Channel Configurations. - Shi-Xuan Zheng; Chung-Yu Yeh; Kuen-Jong Lee; Chen Wang 014; Wu-Tung Cheng; Mark Kassab; Janusz Rajski; Sudhakar M. Reddy (VTS, 2022)

Efficient Test Compression Configuration Selection. - Chong-Siao Ye; Shi-Xuan Zheng; Fong-Jyun Tsai; Chen Wang 014; Kuen-Jong Lee; Wu-Tung Cheng; Sudhakar M. Reddy; Justyna Zawada; Mark Kassab; Janusz Rajski (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)