Extraction of moving object descriptions via differencing. - Sudhakar Yalamanchili; Worthy N. Martin; Jake K. Aggarwal (Comput. Graph. Image Process., 1982)

Algebraic Properties of some Parallel Processor Interconnection Networks. - Sudhakar Yalamanchili; Jake K. Aggarwal (ICDE, 1984)

Workstations in a Local Area Network Environment. - Sudhakar Yalamanchili; Miroslaw Malek; Jake K. Aggarwal (Computer, 1984)

Formulation of parallel image processing tasks. - Sudhakar Yalamanchili; Jake K. Aggarwal (Pattern Recognit. Lett., 1984)

Reconfiguration Strategies for Parallel Architectures. - Sudhakar Yalamanchili; Jake K. Aggarwal (Computer, 1985)

Analysis of a model for parallel image processing. - Sudhakar Yalamanchili; Jake K. Aggarwal (Pattern Recognit., 1985)

A system organization for parallel image processing. - Sudhakar Yalamanchili; Jake K. Aggarwal (Pattern Recognit., 1985)

Parallel image normalization on a mesh connected array processor. - S. Y. Lee; Sudhakar Yalamanchili; Jake K. Aggarwal (Pattern Recognit., 1987)

A Characterization and Analysis of Parallel Processor Interconnection Networks. - Sudhakar Yalamanchili; Jake K. Aggarwal (IEEE Trans. Computers, 1987)

Adaptive routing in generalized hypercube architectures. - Steven D. Young; Sudhakar Yalamanchili (SPDP, 1991)

Parallel Optimization and Execution of Large Join Queries. - Eileen Tien Lin; Edward Omiecinski; Sudhakar Yalamanchili (FGCS, 1992)

Dominant Representations: A Paradigm for Mapping Parallel Computations. - Ajay Mohindra; Sudhakar Yalamanchili (IPPS, 1992)

Pipelined Circuit-Switching: A Fault-Tolerant Variant of Wormhole Routing. - Patrick T. Gaughan; Sudhakar Yalamanchili (SPDP, 1992)

Analytical Models of Bandwidth Allocation in Pipelined k-ary n-cubes. - Patrick T. Gaughan; Sudhakar Yalamanchili (IPPS, 1993)

Partitioning and Mapping a Class of Parallel Multiprocessor Simulation Models. - Hatem Sellami; Sudhakar Yalamanchili (SPDP, 1993)

Genie: An Environment for Partitioning and Mapping in Embedded Multiprocessors. - Sudhakar Yalamanchili; Lynn E. Te Winkel; David L. Perschbacher; Belle Shenoy (SPDP, 1993)

Adaptive Routing Protocols for Hypercube Interconnection Networks. - Patrick T. Gaughan; Sudhakar Yalamanchili (Computer, 1993)

Scouting: Fully Adaptive, Deadlock-Free Routing in Faulty Pipelined Networks. - José Duato; V. B. Dao; Patrick T. Gaughan; Sudhakar Yalamanchili (ICPADS, 1994)

Ariadne - An Adaptive Router for Fault-Tolerant Multicomputers. - James D. Allen; Patrick T. Gaughan; David E. Schimmel; Sudhakar Yalamanchili (ISCA, 1994)

Simulation of Marked Graphs on SIMD Architectures Using Efficient Memory Management. - Hatem Sellami; James D. Allen; David E. Schimmel; Sudhakar Yalamanchili (MASCOTS, 1994)

Partitioning Coarse-Grain Signal Flow Graphs for Heterogeneous DSP Architectures. - Christopher H. de Castro; Sudhakar Yalamanchili (Int. J. Comput. Simul., 1994)

Large Join Optimization on a Hypercube Multiprocessor. - Eileen Tien Lin; Edward Omiecinski; Sudhakar Yalamanchili (IEEE Trans. Knowl. Data Eng., 1994)

Software Based Fault-Tolerant Oblivious Routing in Pipelined Networks. - Young-Joo Suh; Binh Vien Dao; José Duato; Sudhakar Yalamanchili (ICPP (1), 1995)

Time scale combining of conservative parallel discrete event simulations. - Hatem Sellami; Sudhakar Yalamanchili (IPPS, 1995)

Configurable Flow Control Mechanisms for Fault-Tolerant Routing. - Binh Vien Dao; José Duato; Sudhakar Yalamanchili (ISCA, 1995)

Partitioning and mapping in embedded multiprocessor architectures in the presence of constraints. - Sudhakar Yalamanchili; Lynn E. Te Winkel; David L. Perschbacher; Belle Shenoy (Concurr. Pract. Exp., 1995)

A Performance Model of Pipelined K-ary n-cubes. - Patrick T. Gaughan; Sudhakar Yalamanchili (IEEE Trans. Computers, 1995)

Parallelism in Sequential Multiprocessor Simulation Models: A Case Study. - Hatem Sellami; Sudhakar Yalamanchili (ACM Trans. Model. Comput. Simul., 1995)

A Family of Fault-Tolerant Routing Protocols for Direct Multiprocessor Networks. - Patrick T. Gaughan; Sudhakar Yalamanchili (IEEE Trans. Parallel Distributed Syst., 1995)

Incorporating Multi-Chip Module Packaging Constraints into System Design. - Vivek Garg; Steve Lacy; David E. Schimmel; Darrell Stogner; Craig D. Ulmer; D. Scott Wills; Sudhakar Yalamanchili (ED&TC, 1996)

Adaptive resource allocation for embedded parallel applications. - Rakesh Jha; Mustafa Muhammad; Sudhakar Yalamanchili; Karsten Schwan; Daniela Ivan-Rosu; Chris deCastro (HiPC, 1996)

A High Performance Router Architecture for Interconnection Networks. - José Duato; Pedro López 001; Federico Silla; Sudhakar Yalamanchili (ICPP, Vol. 1, 1996)

Algorithms for All-to-All Personalized Exchange in 2D and 3D Tori. - Young-Joo Suh; Sudhakar Yalamanchili (IPPS, 1996)

Optimistic parallel computation: an example from computational chemistry. - Emily Angerer Crawford; Karsten Schwan; Sudhakar Yalamanchili (SPDP, 1996)

Using rapid prototyping in computer architecture design laboratories. - James O. Hamblen; Henry Owen; Sudhakar Yalamanchili; Binh Vien Dao (WCAE@HPCA, 1996)

Paradigms for Modeling and Simulation of Multiprocessor Architectures. - Sudhakar Yalamanchili; Todd Carpenter (Int. J. Comput. Simul., 1996)

Distributed Deadlock-Free Routing in Faulty, Pipelined, Direct Interconnection Networks. - Patrick T. Gaughan; Binh Vien Dao; Sudhakar Yalamanchili; David E. Schimmel (IEEE Trans. Computers, 1996)

Augmented Binary Hypercube: A New Architecture for Processor Management. - Hari Lalgudi; Ian F. Akyildiz; Sudhakar Yalamanchili (IEEE Trans. Computers, 1996)

Interconnection networks - an engineering approach. - José Duato; Sudhakar Yalamanchili; Lionel M. Ni (IEEE, 1997)

Architectural Support for Reducing Communication Overhead in Multiprocessor Interconnection Networks. - Binh Vien Dao; Sudhakar Yalamanchili; José Duato (HPCA, 1997)

Power Constrained Design of Multiprocessor Interconnection Networks. - Chirag S. Patel; Sek M. Chai; Sudhakar Yalamanchili; David E. Schimmel (ICCD, 1997)

Deadlock- and Livelock-Free Routing Protocols for Wave Switching. - José Duato; Pedro López 001; Sudhakar Yalamanchili (IPPS, 1997)

Power/Performance Trade-offs for Direct Networks. - Chirag S. Patel; Sek M. Chai; Sudhakar Yalamanchili; David E. Schimmel (PCRCW, 1997)

On adaptive resource allocation for complex real-time application. - Daniela Rosu 001; Karsten Schwan; Sudhakar Yalamanchili; Rakesh Jha (RTSS, 1997)

FARA - A Framework for Adaptive Resource Allocation in Complex Real-Time Systems. - Daniela Rosu 001; Karsten Schwan; Sudhakar Yalamanchili (IEEE Real Time Technology and Applications Symposium, 1998)

All-To-All Communication with Minimum Start-Up Costs in 2D/3D Tori and Meshes. - Young-Joo Suh; Sudhakar Yalamanchili (IEEE Trans. Parallel Distributed Syst., 1998)

Performance Evaluation of the Multimedia Router with MPEG-2 Video Traffic. - María Blanca Caminero; Francisco J. Quiles 001; José Duato; Damon S. Love; Sudhakar Yalamanchili (CANPC, 1999)

QUIC: A Quality of Service Network Interface Layer for Communication in NOWs. - Richard West; Raj Krishnamurthy; W. K. Norton; Karsten Schwan; Sudhakar Yalamanchili; Marcel-Catalin Rosu; V. Sarat (Heterogeneous Computing Workshop, 1999)

MMR: A High-Performance Multimedia Router - Architecture and Design Trade-Offs. - José Duato; Sudhakar Yalamanchili; María Blanca Caminero; Damon S. Love; Francisco J. Quiles 001 (HPCA, 1999)

Teaching Pipelining and Concurrency using Hardware Description Languages. - Tsai Chi Huang; Sudhakar Yalamanchili; Roy W. Melton; Philip R. Bingham; Cecil O. Alford (MSE, 1999)

Dynamically Configurable Message Flow Control for Fault-Tolerant Routing. - Binh Vien Dao; José Duato; Sudhakar Yalamanchili (IEEE Trans. Parallel Distributed Syst., 1999)

Switch Scheduling in the Multimedia Router (MMR). - Damon S. Love; Sudhakar Yalamanchili; José Duato; María Blanca Caminero; Francisco J. Quiles 001 (IPDPS, 2000)

An Extensible Message Layer for High-Performance Clusters. - Craig D. Ulmer; Sudhakar Yalamanchili (PDPTA, 2000)

Software-Based Rerouting for Fault-Tolerant Pipelined Communication. - Young-Joo Suh; Binh Vien Dao; José Duato; Sudhakar Yalamanchili (IEEE Trans. Parallel Distributed Syst., 2000)

Configurable Algorithms for Complete Exchange in 2D Meshes. - Young-Joo Suh; Sudhakar Yalamanchili (IEEE Trans. Parallel Distributed Syst., 2000)

A Cost-Effective Hardware Link Scheduling Algorithm for the Multimedia Router (MMR). - María Blanca Caminero; Carmen Carrión 001; Francisco J. Quiles 001; José Duato; Sudhakar Yalamanchili (ICN (2), 2001)

Tuning Buffer Size in the Multimedia Router (MMR). - María Blanca Caminero; Carmen Carrión 001; Francisco J. Quiles 001; José Duato; Sudhakar Yalamanchili (IPDPS, 2001)

A new switch scheduling algorithm to improve QoS in the multimedia router. - María Blanca Caminero; Carmen Carrión 001; Francisco J. Quiles 001; José Duato; Sudhakar Yalamanchili (IEEE Workshop on Multimedia Signal Processing, 2002)

Algorithms for Switch-Scheduling in the Multimedia Router for LANs. - Indrani Paul; Sudhakar Yalamanchili; José Duato (HiPC, 2002)

The Customization Landscape for Embedded Systems. - Sudhakar Yalamanchili (HiPC, 2002)

Architecture and Hardware for Scheduling Gigabit Packet Streams. - Raj Krishnamurthy; Sudhakar Yalamanchili; Karsten Schwan; Richard West (Hot Interconnects, 2002)

A multimedia router architecture to provide high performance and QoS guarantees to mixed traffic. - María Blanca Caminero; Carmen Carrión 001; Francisco J. Quiles 001; José Duato; Sudhakar Yalamanchili (ICME (1), 2002)

Investigating Switch Scheduling Algorithms to Support QoS in the Multimedia Router. - María Blanca Caminero; Carmen Carrión 001; Francisco J. Quiles 001; José Duato; Sudhakar Yalamanchili (IPDPS, 2002)

A Tunable Communications Library for Data Injection. - Craig D. Ulmer; Sudhakar Yalamanchili (PDPTA, 2002)

A Solution for Handling Hybrid Traffic in Clustered Environments: The MultiMedia Router MMR. - María Blanca Caminero; Carmen Carrión 001; Francisco J. Quiles 001; José Duato; Sudhakar Yalamanchili (IPDPS, 2003)

Leveraging Block Decisions and Aggregation in the ShareStreams QoS Architecture. - Raj Krishnamurthy; Sudhakar Yalamanchili; Karsten Schwan; Richard West (IPDPS, 2003)

A Hardware Approach to QoS Support in Cluster Environments: The Multimedia Router MMR. - María Blanca Caminero; Carmen Carrión 001; Francisco J. Quiles 001; José Duato; Sudhakar Yalamanchili (PDPTA, 2003)

A Framework for Compiler Driven Design Space Exploration for Embedded System Customization. - Krishna V. Palem; Lakshmi N. Chakrapani; Sudhakar Yalamanchili (ASIAN, 2004)

ShareStreams: A Scalable Architecture and Hardware Support for High-Speed QoS Packet Schedulers. - Raj Krishnamurthy; Sudhakar Yalamanchili; Karsten Schwan; Richard West (FCCM, 2004)

Traffic Scheduling Solutions with QoS Support for an Input-Buffered MultiMedia Router. - María Blanca Caminero; Carmen Carrión 001; Francisco J. Quiles 001; José Duato; Sudhakar Yalamanchili (IEEE Trans. Parallel Distributed Syst., 2005)

Customizable Fault Tolerant Caches for Embedded Processors. - Subramanian Ramaswamy; Sudhakar Yalamanchili (ICCD, 2006)

MMR: A MultiMedia Router architecture to support hybrid workloads. - María Blanca Caminero; Carmen Carrión 001; Francisco J. Quiles 001; José Duato; Sudhakar Yalamanchili (J. Parallel Distributed Comput., 2006)

Data trace cache: an application specific cache architecture. - Subramanian Ramaswamy; Jaswanth Sreeram; Sudhakar Yalamanchili; Krishna V. Palem (SIGARCH Comput. Archit. News, 2006)

Customized Placement for High Performance Embedded Processor Caches. - Subramanian Ramaswamy; Sudhakar Yalamanchili (ARCS, 2007)

Improving cache efficiency via resizing + remapping. - Subramanian Ramaswamy; Sudhakar Yalamanchili (ICCD, 2007)

ShareStreams-V: A Virtualized QoS Packet Scheduling Accelerator. - Kangtao Kendall Chuang; Sudhakar Yalamanchili; Ada Gavrilovska; Karsten Schwan (FCCM, 2008)

An Utilization Driven Framework for Energy Efficient Caches. - Subramanian Ramaswamy; Sudhakar Yalamanchili (HiPC, 2008)

Harmony: an execution model and runtime for heterogeneous many core systems. - Gregory F. Diamos; Sudhakar Yalamanchili (HPDC, 2008)

A methodology for robust, energy efficient design of Spin-Torque-Transfer RAM arrays at scaled technologies. - Subho Chatterjee; Mitchelle Rasquinha; Sudhakar Yalamanchili; Saibal Mukhopadhyay (ICCAD, 2009)

A characterization and analysis of PTX kernels. - Andrew Kerr; Gregory F. Diamos; Sudhakar Yalamanchili (IISWC, 2009)

High Performance Non-blocking Switch Design in 3D Die-Stacking Technology. - Dean L. Lewis; Sudhakar Yalamanchili; Hsien-Hsin S. Lee (ISVLSI, 2009)

Ocelot: a dynamic optimization framework for bulk-synchronous applications in heterogeneous systems. - Gregory Frederick Diamos; Andrew Kerr; Sudhakar Yalamanchili; Nathan Clark (PACT, 2010)

HyVM - Hybrid Virtual Machines - Efficient Use of Future Heterogeneous Chip Multiprocessors. - Karsten Schwan; Ada Gavrilovska; Sudhakar Yalamanchili (ARCS, 2010)

Modeling GPU-CPU workloads and systems. - Andrew Kerr; Gregory F. Diamos; Sudhakar Yalamanchili (GPGPU, 2010)

Dynamic Partitioned Global Address Spaces for power efficient DRAM virtualization. - Jeffrey S. Young 001; Sudhakar Yalamanchili (Green Computing Conference, 2010)

Controller design for tracking induced miss-rates in cache memories. - Nawaf I. Almoosa; Yorai Wardi; Sudhakar Yalamanchili (ICCA, 2010)

Speculative execution on multi-GPU systems. - Gregory F. Diamos; Sudhakar Yalamanchili (IPDPS, 2010)

An energy efficient cache design using spin torque transfer (STT) RAM. - Mitchelle Rasquinha; Dhruv Choudhary; Subho Chatterjee; Saibal Mukhopadhyay; Sudhakar Yalamanchili (ISLPED, 2010)

Regulating Locality vs. Parallelism Tradeoffs in Multiple Memory Controller Environments. - Syed Minhaj Hassan; Dhruv Choudhary; Mitchelle Rasquinha; Sudhakar Yalamanchili (PACT, 2011)

A framework for dynamically instrumenting GPU compute applications within GPU Ocelot. - Naila Farooqui; Andrew Kerr; Gregory Frederick Diamos; Sudhakar Yalamanchili; Karsten Schwan (GPGPU, 2011)

SIMD re-convergence at thread frontiers. - Gregory Frederick Diamos; Benjamin Ashbaugh; Subramaniam Maiyuran; Andrew Kerr; Haicheng Wu; Sudhakar Yalamanchili (MICRO, 2011)

Keeneland: Bringing Heterogeneous GPU Computing to the Computational Science Community. - Jeffrey S. Vetter; Richard Glassbrook; Jack J. Dongarra; Karsten Schwan; Bruce Loftis; Stephen Taylor McNally; Jeremy S. Meredith; James H. Rogers; Philip C. Roth; Kyle Spafford; Sudhakar Yalamanchili (Comput. Sci. Eng., 2011)

A Scalable Design Methodology for Energy Minimization of STTRAM: A Circuit and Architecture Perspective. - Subho Chatterjee; Mitchelle Rasquinha; Sudhakar Yalamanchili; Saibal Mukhopadhyay (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Interconnection Networks. - Sudhakar Yalamanchili (Encyclopedia of Parallel Computing, 2011)

Switching Techniques. - Sudhakar Yalamanchili (Encyclopedia of Parallel Computing, 2011)

A power capping controller for multicore processors. - Nawaf I. Almoosa; William J. Song; Yorai Wardi; Sudhakar Yalamanchili (ACC, 2012)

Throughput regulation in multicore processors via IPA. - Nawaf I. Almoosa; William J. Song; Sudhakar Yalamanchili; Yorai Wardi (CDC, 2012)

Dynamic compilation of data-parallel kernels for vector processors. - Andrew Kerr; Gregory Frederick Diamos; Sudhakar Yalamanchili (CGO, 2012)

Eiger: A framework for the automated synthesis of statistical performance models. - Andrew Kerr; Eric Anger; Gilbert Hendry; Sudhakar Yalamanchili (HiPC, 2012)

Commodity Converged Fabrics for Global Address Spaces in Accelerator Clouds. - Jeffrey S. Young 001; Sudhakar Yalamanchili (HPCC-ICESS, 2012)

Performance impact of virtual machine placement in a datacenter. - Indrani Paul; Sudhakar Yalamanchili; Lizy K. John (IPCCC, 2012)

Optimizing Data Warehousing Applications for GPUs Using Kernel Fusion/Fission. - Haicheng Wu; Gregory F. Diamos; Jin Wang 010; Srihari Cadambi; Sudhakar Yalamanchili; Srimat T. Chakradhar (IPDPS Workshops, 2012)

Lynx: A dynamic instrumentation system for data-parallel applications on GPGPU architectures. - Naila Farooqui; Andrew Kerr; Greg Eisenhauer; Karsten Schwan; Sudhakar Yalamanchili (ISPASS, 2012)

Kernel Weaver: Automatically Fusing Database Primitives for Efficient GPU Computation. - Haicheng Wu; Gregory Frederick Diamos; Srihari Cadambi; Sudhakar Yalamanchili (MICRO, 2012)

A universal parallel front-end for execution driven microarchitecture simulation. - Chad D. Kersey; Arun Rodrigues; Sudhakar Yalamanchili (RAPIDO, 2012)

Designing Configurable, Modifiable and Reusable Components for Simulation of Multicore Systems. - Jun Wang 077; Jesse G. Beu; Sudhakar Yalamanchili; Tom Conte 001 (SC Companion, 2012)

Satisfying Data-Intensive Queries Using GPU Clusters. - Jeffrey S. Young 001; Haicheng Wu; Sudhakar Yalamanchili (SC Companion, 2012)

Instruction-based energy estimation methodology for asymmetric manycore processor simulations. - William J. Song; Sudhakar Yalamanchili; Arun F. Rodrigues; Saibal Mukhopadhyay (SimuTools, 2012)

Characterization and transformation of unstructured control flow in bulk synchronous GPU applications. - Haicheng Wu; Gregory F. Diamos; Jin Wang 010; Si Li; Sudhakar Yalamanchili (Int. J. High Perform. Comput. Appl., 2012)

Accelerating simulation of agent-based models on heterogeneous architectures. - Jin Wang 010; Norman Rubin; Haicheng Wu; Sudhakar Yalamanchili (GPGPU@ASPLOS, 2013)

Oncilla: A GAS runtime for efficient resource allocation and data movement in accelerated clusters. - Jeffrey S. Young 001; Se Hoon Shon; Sudhakar Yalamanchili; Alex Merritt; Karsten Schwan; Holger Fröning (CLUSTER, 2013)

Cooperative boosting: needy versus greedy power management. - Indrani Paul; Srilatha Manne; Manish Arora; William Lloyd Bircher; Sudhakar Yalamanchili (ISCA, 2013)

A Study of the Effect of Partitioning on Parallel Simulation of Multicore Systems. - Zhenjiang Dong; Jun Wang 077; George F. Riley; Sudhakar Yalamanchili (MASCOTS, 2013)

Centralized buffer router: A low latency, low power router for high radix NOCs. - Syed Minhaj Hassan; Sudhakar Yalamanchili (NOCS, 2013)

Optimizing parallel simulation of multicore systems using domain-specific knowledge. - Jun Wang 077; Zhenjiang Dong; Sudhakar Yalamanchili; George F. Riley (SIGSIM-PADS, 2013)

Relational algorithms for multi-bulk-synchronous processors. - Gregory Frederick Diamos; Haicheng Wu; Jin Wang 010; Ashwin Sanjay Lele; Sudhakar Yalamanchili (PPoPP, 2013)

Design space exploration of on-chip ring interconnection for a CPU-GPU heterogeneous architecture. - Jaekyu Lee; Si Li; Hyesoon Kim; Sudhakar Yalamanchili (J. Parallel Distributed Comput., 2013)

Adaptive virtual channel partitioning for network-on-chip in heterogeneous architectures. - Jaekyu Lee; Si Li; Hyesoon Kim; Sudhakar Yalamanchili (ACM Trans. Design Autom. Electr. Syst., 2013)

Efficient Instrumentation of GPGPU Applications Using Information Flow Analysis and Symbolic Execution. - Naila Farooqui; Karsten Schwan; Sudhakar Yalamanchili (GPGPU@ASPLOS, 2014)

ParallelJS: An Execution Framework for JavaScript on Heterogeneous Systems. - Jin Wang 010; Norman Rubin; Sudhakar Yalamanchili (GPGPU@ASPLOS, 2014)

Red Fox: An Execution Environment for Relational Query Processing on GPUs. - Haicheng Wu; Gregory F. Diamos; Tim Sheard; Molham Aref; Sean Baxter; Michael Garland; Sudhakar Yalamanchili (CGO, 2014)

Harmonica: An FPGA-Based Data Parallel Soft Core. - Chad D. Kersey; Sudhakar Yalamanchili; Hyojong Kim; Nimit Nigania; Hyesoon Kim (FCCM, 2014)

Characterization and analysis of dynamic parallelism in unstructured GPU applications. - Jin Wang 010; Sudhakar Yalamanchili (IISWC, 2014)

Energy Introspector: A parallel, composable framework for integrated power-reliability-thermal modeling for multicore architectures. - William J. Song; Saibal Mukhopadhyay; Sudhakar Yalamanchili (ISPASS, 2014)

Manifold: A parallel simulation framework for multicore systems. - Jun Wang 077; Jesse G. Beu; Rishiraj A. Bheda; Tom Conte 001; Zhenjiang Dong; Chad D. Kersey; Mitchelle Rasquinha; George F. Riley; William J. Song; He Xiao; Peng Xu; Sudhakar Yalamanchili (ISPASS, 2014)

Bubble sharing: Area and energy efficient adaptive routers using centralized buffers. - Syed Minhaj Hassan; Sudhakar Yalamanchili (NOCS, 2014)

Architecture-independent modeling of intra-node data movement. - Eric Anger; Sudhakar Yalamanchili; Scott Pakin; Patrick S. McCormick (LLVM@SC, 2014)

An efficient front-end for timing-directed parallel simulation of multi-core system. - Zhenjiang Dong; Jun Wang 077; George F. Riley; Sudhakar Yalamanchili (SimuTools, 2014)

Multipredicate Join Algorithms for Accelerating Relational Graph Processing on GPUs. - Haicheng Wu; Daniel Zinn; Molham Aref; Sudhakar Yalamanchili (ADMS@VLDB, 2014)

Co-design of multicore architectures and microfluidic cooling for 3D stacked ICs. - Zhimin Wan; He Xiao; Yogendra Joshi; Sudhakar Yalamanchili (Microelectron. J., 2014)

Coordinated energy management in heterogeneous processors. - Indrani Paul; Vignesh T. Ravi; Srilatha Manne; Manish Arora; Sudhakar Yalamanchili (Sci. Program., 2014)

Power Modeling for GPU Architectures Using McPAT. - Jieun Lim 001; Nagesh B. Lakshminarayana; Hyesoon Kim; William J. Song; Sudhakar Yalamanchili; Wonyong Sung (ACM Trans. Design Autom. Electr. Syst., 2014)

Control Principles and On-Chip Circuits for Active Cooling Using Integrated Superlattice-Based Thin-Film Thermoelectric Devices. - Borislav Alexandrov; Owen Sullivan; William J. Song; Sudhakar Yalamanchili; Satish Kumar; Saibal Mukhopadhyay (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Temperature regulation in multicore processors using adjustable-gain integral controllers. - Karthik Rao; William J. Song; Sudhakar Yalamanchili; Yorai Wardi (CCA, 2015)

Throughput Regulation in Shared Memory Multicore Processors. - X. Chen; H. Xiao; Yorai Wardi; Sudhakar Yalamanchili (HiPC, 2015)

Application Modeling for Scalable Simulation of Massively Parallel Systems. - Eric Anger; Damian Dechev; Gilbert Hendry; Jeremiah J. Wilke; Sudhakar Yalamanchili (HPCC/CSS/ICESS, 2015)

Managing performance-reliability tradeoffs in multicore processors. - William J. Song; Saibal Mukhopadhyay; Sudhakar Yalamanchili (IRPS, 2015)

Harmonia: balancing compute and memory power in high-performance GPUs. - Indrani Paul; Wei Huang 004; Manish Arora; Sudhakar Yalamanchili (ISCA, 2015)

Dynamic thread block launch: a lightweight execution mechanism to support irregular applications on GPUs. - Jin Wang 010; Norm Rubin; Albert Sidelnik; Sudhakar Yalamanchili (ISCA, 2015)

Near Data Processing: Impact and Optimization of 3D Memory System Architecture on the Uncore. - Syed Minhaj Hassan; Sudhakar Yalamanchili; Saibal Mukhopadhyay (MEMSYS, 2015)

SIMT-based Logic Layers for Stacked DRAM Architectures: A Prototype. - Chad D. Kersey; Sudhakar Yalamanchili; Hyesoon Kim (MEMSYS, 2015)

Understanding Energy Aspects of Processing-near-Memory for HPC Workloads. - Hyojong Kim; Hyesoon Kim; Sudhakar Yalamanchili; Arun F. Rodrigues (MEMSYS, 2015)

Architectural Reliability: Lifetime Reliability Characterization and Management ofMany-Core Processors. - William J. Song; Saibal Mukhopadhyay; Sudhakar Yalamanchili (IEEE Comput. Archit. Lett., 2015)

Amdahl's law for lifetime reliability scaling in heterogeneous multicore processors. - William J. Song; Saibal Mukhopadhyay; Sudhakar Yalamanchili (HPCA, 2016)

Neurocube: A Programmable Digital Neuromorphic Architecture with High-Density 3D Memory. - Duckhwan Kim 001; Jaeha Kung; Sek M. Chai; Sudhakar Yalamanchili; Saibal Mukhopadhyay (ISCA, 2016)

LaPerm: Locality Aware Scheduler for Dynamic Parallelism on GPUs. - Jin Wang 010; Norm Rubin; Albert Sidelnik; Sudhakar Yalamanchili (ISCA, 2016)

Understanding the Impact of Air and Microfluidics Cooling on Performance of 3D Stacked Memory Systems. - Syed Minhaj Hassan; Sudhakar Yalamanchili (MEMSYS, 2016)

General-purpose join algorithms for large graph triangle listing on heterogeneous systems. - Daniel Zinn; Haicheng Wu; Jin Wang 010; Molham Aref; Sudhakar Yalamanchili (GPGPU@PPoPP, 2016)

Power-Constrained Performance Scheduling of Data Parallel Tasks. - Eric Anger; Jeremiah J. Wilke; Sudhakar Yalamanchili (E2SC@SC, 2016)

IPA in the loop: Control design for throughput regulation in computer processors. - Xinwei Chen; Yorai Wardi; Sudhakar Yalamanchili (WODES, 2016)

Thermally Adaptive Cache Access Mechanisms for 3D Many-Core Architectures. - He Xiao; Wen Yueh; Saibal Mukhopadhyay; Sudhakar Yalamanchili (IEEE Comput. Archit. Lett., 2016)

FNM: An Enhanced Null-Message Algorithm for Parallel Simulation of Multicore Systems. - Jun Wang 077; Zhenjiang Dong; Sudhakar Yalamanchili; George F. Riley (ACM Trans. Model. Comput. Simul., 2016)

Power regulation in high performance multicore processors. - Xinwei Chen; Yorai Wardi; Sudhakar Yalamanchili (CDC, 2017)

Application-Specific Performance-Aware Energy Optimization on Android Mobile Devices. - Karthik Rao; Jun Wang 077; Sudhakar Yalamanchili; Yorai Wardi; Handong Ye (HPCA, 2017)

Demystifying the characteristics of 3D-stacked memories: A case study for Hybrid Memory Cube. - Ramyad Hadidi; Bahar Asgari; Burhan Ahmad Mudassar; Saibal Mukhopadhyay; Sudhakar Yalamanchili; Hyesoon Kim (IISWC, 2017)

Lightweight SIMT core designs for intelligent 3D stacked DRAM. - Chad D. Kersey; Hyesoon Kim; Sudhakar Yalamanchili (MEMSYS, 2017)

Pagevault: securing off-chip memory using page-based authentication. - Blaise-Pascal Tine; Sudhakar Yalamanchili (MEMSYS, 2017)

Power Regulation in High Performance Multicore Processors. - X. Chen; Yorai Wardi; Sudhakar Yalamanchili (CoRR, 2017)

NeuroTrainer: An Intelligent Memory Module for Deep Learning Training. - Duckhwan Kim 001; Taesik Na; Sudhakar Yalamanchili; Saibal Mukhopadhyay (CoRR, 2017)

Slim NoC: A Low-Diameter On-Chip Network Topology for High Energy Efficiency and Scalability. - Maciej Besta; Syed Minhaj Hassan; Sudhakar Yalamanchili; Rachata Ausavarungnirun; Onur Mutlu; Torsten Hoefler (ASPLOS, 2018)

A ferroelectric FET based power-efficient architecture for data-intensive computing. - Yun Long; Taesik Na; Prakshi Rastogi; Karthik Rao; Asif Islam Khan; Sudhakar Yalamanchili; Saibal Mukhopadhyay (ICCAD, 2018)

Memory Slices: A Modular Building Block for Scalable, Intelligent Memory Systems. - Bahar Asgari; Saibal Mukhopadhyay; Sudhakar Yalamanchili (CoRR, 2018)

TRINITY: Coordinated Performance, Energy and Temperature Management in 3D Processor-Memory Stacks. - Karthik Rao; William J. Song; Yorai Wardi; Sudhakar Yalamanchili (CoRR, 2018)

Instruction-throughput regulation in computer processors with data-center applications. - Xinwei Chen; Yorai Wardi; Sudhakar Yalamanchili (Discret. Event Dyn. Syst., 2018)

DeepTrain: A Programmable Embedded Platform for Training Deep Neural Networks. - Duckhwan Kim 001; Taesik Na; Sudhakar Yalamanchili; Saibal Mukhopadhyay (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

POSTER: Tango: An Optimizing Compiler for Just-In-Time RTL Simulation. - Blaise-Pascal Tine; Sudhakar Yalamanchili; Hyesoon Kim; Jeffrey S. Vetter (PACT, 2019)

LODESTAR: Creating Locally-Dense CNNs for Efficient Inference on Systolic Arrays. - Bahar Asgari; Ramyad Hadidi; Hyesoon Kim; Sudhakar Yalamanchili (DAC, 2019)

Heterogeneous integration for artificial intelligence: Challenges and opportunities. - Saibal Mukhopadhyay; Yun Long; Burhan Ahmad Mudassar; C. S. Nair; Bartlet H. DeProspo; Hakki Mert Torun; M. Kathaperumal; V. Smet; Duckhwan Kim 001; Sudhakar Yalamanchili; Madhavan Swaminathan (IBM J. Res. Dev., 2019)

ERIDANUS: Efficiently Running Inference of DNNs Using Systolic Arrays. - Bahar Asgari; Ramyad Hadidi; Hyesoon Kim; Sudhakar Yalamanchili (IEEE Micro, 2019)

Tango: An Optimizing Compiler for Just-In-Time RTL Simulation. - Blaise-Pascal Tine; Sudhakar Yalamanchili; Hyesoon Kim (DATE, 2020)

ALRESCHA: A Lightweight Reconfigurable Sparse-Computation Accelerator. - Bahar Asgari; Ramyad Hadidi; Tushar Krishna; Hyesoon Kim; Sudhakar Yalamanchili (HPCA, 2020)

VDPred: Predicting Voltage Droop for Power-Effient 3D Multi-core Processor Design. - He Xiao; Monodeep Kar; Saibal Mukhopadhyay; Sudhakar Yalamanchili (ICCAE, 2021)

Efficiently Solving Partial Differential Equations in a Partially Reconfigurable Specialized Hardware. - Bahar Asgari; Ramyad Hadidi; Tushar Krishna; Hyesoon Kim; Sudhakar Yalamanchili (IEEE Trans. Computers, 2021)

MAHASIM: Machine-Learning Hardware Acceleration Using a Software-Defined Intelligent Memory System. - Bahar Asgari; Saibal Mukhopadhyay; Sudhakar Yalamanchili (J. Signal Process. Syst., 2021)