Implementation and Performance Evaluation of Novel Line Adder Architecture for Portable Systems : A Vedic Mathematics Approach. - Sudhanshu Janwadkar; Rasika Dhavse (TENCON, 2020)

Investigation and Analysis of Power Performance Area (PPA) Cards of Digital Multiplier Architectures. - Sudhanshu Janwadkar; Rasika Dhavse (J. Circuits Syst. Comput., 2022)

ASIC design of power and area efficient programmable FIR filter using optimized Urdhva-Tiryagbhyam Multiplier for impedance cardiography. - Sudhanshu Janwadkar; Rasika Dhavse (Microprocess. Microsystems, 2024)

ASIC implementation of ECG denoising FIR filter by using hybrid Vedic-Wallace tree multiplier. - Sudhanshu Janwadkar; Rasika Dhavse (Int. J. Circuit Theory Appl., 2024)