Team [Ii][Ss][Uu][0-2]{4} design overview: MEMOCODE 2010 design contest. - Sudhanshu Vyas; Pooja Mhapsekar; Aditya Ashok; Moinuddin Sayed; Avinash Srinivasa; Gunjan Pandey; Adam Jackson; Matthew Nelson; Anand Saggi; Harini Sundararaman; Phillip H. Jones (MEMOCODE, 2010)

Design and evaluation of a delay-based FPGA Physically Unclonable Function. - Aaron Mills; Sudhanshu Vyas; Michael Patterson; Christopher Sabotta; Phillip H. Jones; Joseph Zambreno (ICCD, 2012)

Improving System Predictability and Performance via Hardware Accelerated Data Structures. - Chetan Kumar Ng; Sudhanshu Vyas; Jonathan A. Shidal; Ron K. Cytron; Christopher D. Gill; Joseph Zambreno; Phillip H. Jones (ICCS, 2012)

Scheduling Challenges in Mixed Critical Real-Time Heterogeneous Computing Platforms. - Chetan Kumar Ng; Sudhanshu Vyas; Ron K. Cytron; Christopher D. Gill; Joseph Zambreno; Phillip H. Jones (ICCS, 2013)

Hardware architectural support for control systems and sensor processing. - Sudhanshu Vyas; Adwait Gupte; Christopher D. Gill; Ron K. Cytron; Joseph Zambreno; Phillip H. Jones (ACM Trans. Embed. Comput. Syst., 2013)

Cache design for mixed criticality real-time systems. - N. G. Chetan Kumar; Sudhanshu Vyas; Ron K. Cytron; Christopher D. Gill; Joseph Zambreno; Phillip H. Jones (ICCD, 2014)

An FPGA-Based Plant-on-Chip Platform for Cyber-Physical System Analysis. - Sudhanshu Vyas; Chetan Kumar Ng; Joseph Zambreno; Christopher D. Gill; Ron Cytron; Phillip H. Jones (IEEE Embed. Syst. Lett., 2014)

Hardware-software architecture for priority queue management in real-time and embedded systems. - N. G. Chetan Kumar; Sudhanshu Vyas; Ron K. Cytron; Christopher D. Gill; Joseph Zambreno; Phillip H. Jones (Int. J. Embed. Syst., 2014)

A software configurable coprocessor-based state-space controller. - Aaron Mills; Pei Zhang 009; Sudhanshu Vyas; Joseph Zambreno; Phillip H. Jones (FPL, 2015)

A Fault-Aware Toolchain Approach for FPGA Fault Tolerance. - Adwait Gupte; Sudhanshu Vyas; Phillip H. Jones (ACM Trans. Design Autom. Electr. Syst., 2015)