Testing of Analog Neural Array-Processor Chips. - Wen-Jay Hsu; Bing J. Sheu; Sudhir M. Gowda (ICCD, 1991)

Design of reliable VLSI circuits using simulation techniques. - Wen-Jay Hsu; Bing J. Sheu; Sudhir M. Gowda (IEEE J. Solid State Circuits, 1991)

Advanced integrated-circuit reliability simulation including dynamic stress effects. - Wen-Jay Hsu; Bing J. Sheu; Sudhir M. Gowda; Chang-Gyu Hwang (IEEE J. Solid State Circuits, 1992)

Design and characterization of analog VLSI neural network modules. - Sudhir M. Gowda; Bing J. Sheu; Joongho Choi; Chang-Gyu Hwang; James S. Cable (IEEE J. Solid State Circuits, 1993)

BSIM plus: an advanced SPICE model for submicron MOS VLSI circuits. - Sudhir M. Gowda; Bing J. Sheu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

Testing of programmable analog neural network chips. - Sudhir M. Gowda; Bing J. Sheu; Wen-Jay Hsu (J. VLSI Signal Process., 1994)

Custom design of CMOS low-power high-performance digital signal-processing macro for hard-disk-drive applications. - Hyun J. Shin; Dale J. Pearson; Scott K. Reynolds; Andrew C. Megdanis; Sudhir M. Gowda; Kevin R. Wrenner (IBM J. Res. Dev., 1995)

Digital FIR filters for high speed PRML disk read channels. - Dale J. Pearson; Scott K. Reynolds; Andrew C. Megdanis; Sudhir M. Gowda; Kevin R. Wrenner; Michael Immediato; Richard L. Galbraith; Hyun J. Shin (IEEE J. Solid State Circuits, 1995)

A 10-Gb/s CMOS clock and data recovery circuit using a secondary delay-locked loop. - Woogeun Rhee; Herschel A. Ainspan; Sergey V. Rylov; Alexander V. Rylyakov; Michael P. Beakes; Daniel J. Friedman; Sudhir M. Gowda; Mehmet Soyuer (CICC, 2003)

Integrated transversal equalizers in high-speed fiber-optic systems. - Hui Wu; José A. Tierno; Petar K. Pepeljugoski; Jeremy Schaub; Sudhir M. Gowda; Jeffrey A. Kash; Ali Hajimiri (IEEE J. Solid State Circuits, 2003)

10+ Gb/s 90nm CMOS serial link demo in CBGA package. - Sergey V. Rylov; Scott K. Reynolds; Daniel W. Storaska; Brian A. Floyd; Mohit Kapur; Thomas Zwick; Sudhir M. Gowda; Michael Sorna (CICC, 2004)

10+ gb/s 90-nm CMOS serial link demo in CBGA package. - Sergey V. Rylov; Scott K. Reynolds; Daniel W. Storaska; Brian A. Floyd; Mohit Kapur; Thomas Zwick; Sudhir M. Gowda; Michael Sorna (IEEE J. Solid State Circuits, 2005)

A 10Gb/s 5-Tap-DFE/4-Tap-FFE Transceiver in 90nm CMOS. - Mounir Meghelli; Sergey V. Rylov; John F. Bulzacchelli; Woogeun Rhee; Alexander V. Rylyakov; Herschel A. Ainspan; Benjamin D. Parker; Michael P. Beakes; Aichin Chung; Troy J. Beukema; Petar K. Pepeljugoski; L. Shan; et al. (ISSCC, 2006)

A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology. - John F. Bulzacchelli; Mounir Meghelli; Sergey V. Rylov; Woogeun Rhee; Alexander V. Rylyakov; Herschel A. Ainspan; Benjamin D. Parker; Michael P. Beakes; Aichin Chung; Troy J. Beukema; Petar K. Pepeljugoski; Lei Shan; et al. (IEEE J. Solid State Circuits, 2006)