Quality and complexity comparison of H.264 intra mode with JPEG2000 and JPEG. - Aravind Al; Bindu P. Rao; Sudhir S. Kudva; Sreenu Babu; David S. Sumam; Ajit V. Rao (ICIP, 2004)

A Low Power Frequency Multiplication Technique for ZigBee Transciever. - Jagdish Nayayan Pandey; Sudhir S. Kudva; Bharadwaj Amrutur (VLSI Design, 2007)

Quadrature generation techniques for frequency multiplication based oscillators. - Jagdish Nayayan Pandey; Bharadwaj Amrutur; Sudhir S. Kudva (ISCAS, 2008)

Fully-Integrated On-Chip DC-DC Converter With a 450X Output Range. - Sudhir S. Kudva; Ramesh Harjani (IEEE J. Solid State Circuits, 2011)

Fully integrated capacitive converter with all digital ripple mitigation. - Sudhir S. Kudva; Ramesh Harjani (CICC, 2012)

Fully Integrated Capacitive DC-DC Converter With All-Digital Ripple Mitigation Technique. - Sudhir S. Kudva; Ramesh Harjani (IEEE J. Solid State Circuits, 2013)

High power-density, hybrid inductive/capacitive converter with area reuse for multi-domain DVS. - Sudhir S. Kudva; Saurabh Chaubey; Ramesh Harjani (CICC, 2014)

Modeling and Analysis of Power Supply Noise Tolerance with Fine-Grained GALS Adaptive Clocks. - Divya Akella Kamakshi; Matthew Fojtik; Brucek Khailany; Sudhir S. Kudva; Yaping Zhou; Benton H. Calhoun (ASYNC, 2016)

A switching linear regulator based on a fast-self-clocked comparator with very low probability of meta-stability and a parallel analog ripple control module. - Sudhir S. Kudva; Sanquan Song; John W. Poulton; John M. Wilson 002; Wenxu Zhao; C. Thomas Gray (CICC, 2018)

Ground-referenced signaling for intra-chip and short-reach chip-to-chip interconnects. - Walker J. Turner; John W. Poulton; John M. Wilson 002; Xi Chen 033; Stephen G. Tell; Matthew Fojtik; Thomas H. Greer; Brian Zimmer; Sanquan Song; Nikola Nedovic; Sudhir S. Kudva; Sunil R. Sudhakaran; et al. (CICC, 2018)

A 1.17pJ/b 25Gb/s/pin ground-referenced single-ended serial link for off- and on-package communication in 16nm CMOS using a process- and temperature-adaptive voltage regulator. - John M. Wilson 002; Walker J. Turner; John W. Poulton; Brian Zimmer; Xi Chen 033; Sudhir S. Kudva; Sanquan Song; Stephen G. Tell; Nikola Nedovic; Wenxu Zhao; Sunil R. Sudhakaran; C. Thomas Gray; et al. (ISSCC, 2018)

A 2-to-20 GHz Multi-Phase Clock Generator with Phase Interpolators Using Injection-Locked Oscillation Buffers for High-Speed IOs in 16nm FinFET. - Sanquan Song; John Poulton; Xi Chen 033; Brian Zimmer; Stephen G. Tell; Walker J. Turner; Sudhir S. Kudva; Nikola Nedovic; John M. Wilson 002; C. Thomas Gray; William J. Dally (CICC, 2019)

A 1.17-pJ/b, 25-Gb/s/pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication Using a Process- and Temperature-Adaptive Voltage Regulator. - John W. Poulton; John M. Wilson 002; Walker J. Turner; Brian Zimmer; Xi Chen 033; Sudhir S. Kudva; Sanquan Song; Stephen G. Tell; Nikola Nedovic; Wenxu Zhao; Sunil R. Sudhakaran; C. Thomas Gray; et al. (IEEE J. Solid State Circuits, 2019)

6.6 Reference-Noise Compensation Scheme for Single-Ended Package-to-Package Links. - Xi Chen 033; Nikola Nedovic; Stephen G. Tell; Sudhir S. Kudva; Brian Zimmer; Thomas H. Greer; John W. Poulton; Sanquan Song; Walker J. Turner; John M. Wilson 002; C. Thomas Gray (ISSCC, 2020)

An FLL-Based Clock Glitch Detector for Security Circuits in a 5nm FINFET Process. - Sanquan Song; Stephen G. Tell; Brian Zimmer; Sudhir S. Kudva; Nikola Nedovic; C. Thomas Gray (VLSI Technology and Circuits, 2022)

A Distributed Power Supply Scheme with Dropout Voltage in Range 6mv-500mv and a Low Overhead Retention Mode. - Siddharth Saxena; Sudhir S. Kudva; Vijay Srinivasan; Miguel Rodriguez; Walter Li; Shalimar Rasheed; Gaurav Ajwani; Tezaswi Raja; Santosh A; C. Thomas Gray (CICC, 2024)

16.4 High-Density and Low-Power PUF Designs in 5nm Achieving 23× and 39× BER Reduction After Unstable Bit Detection and Masking. - Sudhir S. Kudva; Mahmut Ersin Sinangil; Stephen G. Tell; Nikola Nedovic; Sanquan Song; Brian Zimmer; C. Thomas Gray (ISSCC, 2024)

17.6 A 100MHz Self-Calibrating RC Oscillator Capable of Clock-Glitch Detection for Hardware Security in a 3nm FinFET Process. - Nandish Mehta; Stephen G. Tell; Sanquan Song; Sudhir S. Kudva; Brian Zimmer; Mahmut E. Sinangil; C. Thomas Gray (ISSCC, 2025)