Low power interconnects for SIMD computers. - Mark Woh; Sudhir Satpathy; Ronald G. Dreslinski; Danny Kershaw; Dennis Sylvester; David T. Blaauw; Trevor N. Mudge (DATE, 2011)

XPoint cache: scaling existing bus-based coherence protocols for 2D and 3D many-core systems. - Ronald G. Dreslinski; Thomas Manville; Korey Sewell; Reetuparna Das; Nathaniel Ross Pinckney; Sudhir Satpathy; David T. Blaauw; Dennis Sylvester; Trevor N. Mudge (PACT, 2012)

High radix self-arbitrating switch fabric with multiple arbitration schemes and quality of service. - Sudhir Satpathy; Reetuparna Das; Ronald G. Dreslinski; Trevor N. Mudge; Dennis Sylvester; David T. Blaauw (DAC, 2012)

Swizzle Switch: A self-arbitrating high-radix crossbar for NoC systems. - Ronald G. Dreslinski; Korey Sewell; Thomas Manville; Sudhir Satpathy; Nathaniel Ross Pinckney; Geoffrey Blake; Michael Cieslak; Reetuparna Das; Thomas F. Wenisch; Dennis Sylvester; David T. Blaauw; Trevor N. Mudge (Hot Chips Symposium, 2012)

Centip3De: A 3930DMIPS/W configurable near-threshold 3D stacked system with 64 ARM Cortex-M3 cores. - David Fick; Ronald G. Dreslinski; Bharan Giridhar; Gyouho Kim; Sangwon Seo; Matthew Fojtik; Sudhir Satpathy; Yoonmyung Lee; Daeyeon Kim; Nurrachman Liu; Michael Wieckowski; Gregory K. Chen; et al. (ISSCC, 2012)

A 4.5Tb/s 3.4Tb/s/W 64×64 switch fabric with self-updating least-recently-granted priority and quality-of-service arbitration in 45nm CMOS. - Sudhir Satpathy; Korey Sewell; Thomas Manville; Yen-Po Chen; Ronald G. Dreslinski; Dennis Sylvester; Trevor N. Mudge; David T. Blaauw (ISSCC, 2012)

A standard cell compatible bidirectional repeater with thyristor assist. - Sudhir Satpathy; Dennis Sylvester; David T. Blaauw (VLSIC, 2012)

Swizzle-Switch Networks for Many-Core Systems. - Korey Sewell; Ronald G. Dreslinski; Thomas Manville; Sudhir Satpathy; Nathaniel Ross Pinckney; Geoffrey Blake; Michael Cieslak; Reetuparna Das; Thomas F. Wenisch; Dennis Sylvester; David T. Blaauw; Trevor N. Mudge (IEEE J. Emerg. Sel. Topics Circuits Syst., 2012)

2.4 Gbps, 7 mW All-Digital PVT-Variation Tolerant True Random Number Generator for 45 nm CMOS High-Performance Microprocessors. - Sanu Mathew; Suresh Srinivasan; Mark A. Anders 001; Himanshu Kaul; Steven Hsu; Farhana Sheikh; Amit Agarwal 001; Sudhir Satpathy; Ram Krishnamurthy 001 (IEEE J. Solid State Circuits, 2012)

Catnap: energy proportional multiple network-on-chip. - Reetuparna Das; Satish Narayanasamy; Sudhir Satpathy; Ronald G. Dreslinski (ISCA, 2013)

Centip3De: a many-core prototype exploring 3D integration and near-threshold computing. - Ronald G. Dreslinski; David Fick; Bharan Giridhar; Gyouho Kim; Sangwon Seo; Matthew Fojtik; Sudhir Satpathy; Yoonmyung Lee; Daeyeon Kim; Nurrachman Liu; Michael Wieckowski; Gregory K. Chen; et al. (Commun. ACM, 2013)

Centip3De: A Cluster-Based NTC Architecture With 64 ARM Cortex-M3 Cores in 3D Stacked 130 nm CMOS. - David Fick; Ronald G. Dreslinski; Bharan Giridhar; Gyouho Kim; Sangwon Seo; Matthew Fojtik; Sudhir Satpathy; Yoonmyung Lee; Daeyeon Kim; Nurrachman Liu; Michael Wieckowski; Gregory K. Chen; et al. (IEEE J. Solid State Circuits, 2013)

Centip3De: A 64-Core, 3D Stacked Near-Threshold System. - Ronald G. Dreslinski; David Fick; Bharan Giridhar; Gyouho Kim; Sangwon Seo; Matthew Fojtik; Sudhir Satpathy; Yoonmyung Lee; Daeyeon Kim; Nurrachman Liu; Michael Wieckowski; Gregory K. Chen; et al. (IEEE Micro, 2013)

13fJ/bit probing-resilient 250K PUF array with soft darkbit masking for 1.94% bit-error in 22nm tri-gate CMOS. - Sudhir Satpathy; Sanu Mathew; Jiangtao Li 001; Patrick Koeberl; Mark A. Anders 001; Himanshu Kaul; Gregory K. Chen; Amit Agarwal 001; Steven Hsu; Ram Krishnamurthy 001 (ESSCIRC, 2014)

16.1 A 340mV-to-0.9V 20.2Tb/s source-synchronous hybrid packet/circuit-switched 16×16 network-on-chip in 22nm tri-gate CMOS. - Gregory K. Chen; Mark A. Anders 001; Himanshu Kaul; Sudhir Satpathy; Sanu K. Mathew; Steven K. Hsu; Amit Agarwal 001; Ram K. Krishnamurthy; Shekhar Borkar; Vivek De (ISSCC, 2014)

16.2 A 0.19pJ/b PVT-variation-tolerant hybrid physically unclonable function circuit for 100% stable secure key generation in 22nm CMOS. - Sanu K. Mathew; Sudhir Satpathy; Mark A. Anders 001; Himanshu Kaul; Steven K. Hsu; Amit Agarwal 001; Gregory K. Chen; Rachael J. Parker; Ram K. Krishnamurthy; Vivek De (ISSCC, 2014)

340mV-1.1V, 289Gbps/W, 2090-gate NanoAES hardware accelerator with area-optimized encrypt/decrypt GF(24)2 polynomials in 22nm tri-gate CMOS. - Sanu Mathew; Sudhir Satpathy; Vikram B. Suresh; Himanshu Kaul; Mark A. Anders 001; Gregory K. Chen; Amit Agarwal 001; Steven Hsu; Ram Krishnamurthy 001 (VLSIC, 2014)

μRNG: A 300-950mV 323Gbps/W all-digital full-entropy true random number generator in 14nm FinFET CMOS. - Sanu Mathew; David Johnston; Paul Newman 002; Sudhir Satpathy; Vikram B. Suresh; Mark A. Anders 001; Himanshu Kaul; Gregory K. Chen; Amit Agarwal 001; Steven Hsu; Ram Krishnamurthy 001 (ESSCIRC, 2015)

A 340 mV-to-0.9 V 20.2 Tb/s Source-Synchronous Hybrid Packet/Circuit-Switched 16 × 16 Network-on-Chip in 22 nm Tri-Gate CMOS. - Gregory K. Chen; Mark A. Anders 001; Himanshu Kaul; Sudhir Satpathy; Sanu K. Mathew; Steven Hsu; Amit Agarwal 001; Ram Krishnamurthy 001; Vivek De; Shekhar Borkar (IEEE J. Solid State Circuits, 2015)

340 mV-1.1 V, 289 Gbps/W, 2090-Gate NanoAES Hardware Accelerator With Area-Optimized Encrypt/Decrypt GF(2 4 ) 2 Polynomials in 22 nm Tri-Gate CMOS. - Sanu Mathew; Sudhir Satpathy; Vikram B. Suresh; Mark A. Anders 001; Himanshu Kaul; Amit Agarwal 001; Steven Hsu; Gregory K. Chen; Ram Krishnamurthy 001 (IEEE J. Solid State Circuits, 2015)

A 305mV-850mV 400μW 45GSamples/J reconfigurable compressive sensing engine with early-termination for ultra-low energy target detection in 14nm tri-gate CMOS. - Sudhir Satpathy; Sanu Mathew; Vikram B. Suresh; Mark A. Anders 001; Gregory K. Chen; Himanshu Kaul; Amit Agarwal 001; Steven Hsu; Ram Krishnamurthy 001; Vivek De (A-SSCC, 2016)

Ultra-low energy security circuits for IoT applications. - Sudhir Satpathy; Sanu Mathew; Vikram B. Suresh; Ram Krishnamurthy 001 (ICCD, 2016)

14.4 A 21.5M-query-vectors/s 3.37nJ/vector reconfigurable k-nearest-neighbor accelerator with adaptive precision in 14nm tri-gate CMOS. - Himanshu Kaul; Mark A. Anders 001; Sanu K. Mathew; Gregory K. Chen; Sudhir Satpathy; Steven Hsu; Amit Agarwal 001; Ram Krishnamurthy 001 (ISSCC, 2016)

A 350mV-900mV 2.1GHz 0.011mm2 regular expression matching accelerator with aging-tolerant low-VMIN circuits in 14nm tri-gate CMOS. - Amit Agarwal 001; Steven Hsu; Mark A. Anders 001; Sanu Mathew; Gregory K. Chen; Himanshu Kaul; Sudhir Satpathy; Ram Krishnamurthy 001 (VLSI Circuits, 2016)

A 4fJ/bit delay-hardened physically unclonable function circuit with selective bit destabilization in 14nm tri-gate CMOS. - Sanu Mathew; Sudhir Satpathy; Vikram B. Suresh; Mark A. Anders 001; Himanshu Kaul; Amit Agarwal 001; Steven Hsu; Gregory K. Chen; Ram Krishnamurthy 001; Vivek De (VLSI Circuits, 2016)

250mV-950mV 1.1Tbps/W double-affine mapped Sbox based composite-field SMS4 encrypt/decrypt accelerator in 14nm tri-gate CMOS. - Sudhir Satpathy; Sanu Mathew; Vikram B. Suresh; Mark A. Anders 001; Himanshu Kaul; Amit Agarwal 001; Steven Hsu; Gregory K. Chen; Ram Krishnamurthy 001 (VLSI Circuits, 2016)

µRNG: A 300-950 mV, 323 Gbps/W All-Digital Full-Entropy True Random Number Generator in 14 nm FinFET CMOS. - Sanu K. Mathew; David Johnston; Sudhir Satpathy; Vikram B. Suresh; Paul Newman 002; Mark A. Anders 001; Himanshu Kaul; Amit Agarwal 001; Steven Hsu; Gregory K. Chen; Ram K. Krishnamurthy (IEEE J. Solid State Circuits, 2016)

Energy efficient and ultra low voltage security circuits for nanoscale CMOS technologies. - Sanu Mathew; Sudhir Satpathy; Vikram B. Suresh; Ram K. Krishnamurthy (CICC, 2017)

Invited paper: Ultra-low energy security circuit primitives for IoT platforms. - Sanu Mathew; Sudhir Satpathy; Vikram B. Suresh; Ram Krishnamurthy 001 (ISLPED, 2017)

A 4-fJ/b Delay-Hardened Physically Unclonable Function Circuit With Selective Bit Destabilization in 14-nm Trigate CMOS. - Sudhir Satpathy; Sanu K. Mathew; Vikram B. Suresh; Mark A. Anders 001; Himanshu Kaul; Amit Agarwal 001; Steven Hsu; Gregory K. Chen; Ram K. Krishnamurthy; Vivek K. De (IEEE J. Solid State Circuits, 2017)

Ultra-Lightweight 548-1080 Gate 166Gbps/W-12.6Tbps/W SIMON 32/64 Cipher Accelerators for IoT in 14nm Tri-gate CMOS. - Himanshu Kaul; Mark A. Anders 001; Sanu Mathew; Vikram B. Suresh; Sudhir Satpathy; Amit Agarwal 001; Steven Hsu; Ram Krishnamurthy 001 (A-SSCC, 2018)

A 280mV 3.1pJ/code Huffman Decoder for DEFLATE Decompression Featuring Opportunistic Code Skip and 3-way Symbol Generation in 14nm Tri-gate CMOS. - Sudhir Satpathy; Sanu Mathew; Vikram B. Suresh; Vinodh Gopal; James Guilford; Mark A. Anders 001; Himanshu Kaul; Amit Agarwal 001; Steven Hsu; Ram Krishnamurthy 001 (A-SSCC, 2018)

Ultra-low energy circuit building blocks for security technologies. - Sanu Mathew; Sudhir Satpathy; Vikram B. Suresh; Ram Krishnamurthy 001 (DATE, 2018)

34.4Mbps 1.56Tbps/W DEFLATE Decompression Accelerator Featuring Block-Adaptive Huffman Decoder in 14nm Tri-Gate CMOS for IoT Platforms. - Sudhir Satpathy; Sanu Mathew; Vikram B. Suresh; Vinodh Gopal; James Guilford; Mark A. Anders 001; Himanshu Kaul; Amit Agarwal 001; Steven Hsu; Kam Krisnnamurthy (ESSCIRC, 2018)

A 230mV-950mV 2.8Tbps/W Unified SHA256/SM3 Secure Hashing Hardware Accelerator in 14nm Tri-Gate CMOS. - Vikram B. Suresh; Sudhir Satpathy; Sanu Mathew; Mark A. Anders 001; Himanshu Kaul; Amit Agarwal 001; Steven Hsu; Ram Krishnamurthy 001 (ESSCIRC, 2018)

2.9TOPS/W Reconfigurable Dense/Sparse Matrix-Multiply Accelerator with Unified INT8/INTI6/FP16 Datapath in 14NM Tri-Gate CMOS. - Mark A. Anders 001; Himanshu Kaul; Sanu Mathew; Vikram B. Suresh; Sudhir Satpathy; Amit Agarwal 001; Steven Hsu; Ram Krishnamurthy 001 (VLSI Circuits, 2018)

An All-Digital Unified Static/Dynamic Entropy Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction for Secure Privacy-Preserving Mutual Authentication in IoT Mote Platforms. - Sudhir Satpathy; Sanu Mathew; Vikram B. Suresh; Mark A. Anders 001; Himanshu Kaul; Amit Agarwal 001; Steven Hsu; Ram Krishnamurthy 001; Vivek De (VLSI Circuits, 2018)

220MV-900MV 794/584/754 GBPS/W Reconfigurable GF(24)2 AES/SMS4/Camellia Symmetric-Key Cipher Accelerator in 14NM Tri-Gate CMOS. - Sudhir Satpathy; Vikram B. Suresh; Sanu Mathew; Mark A. Anders 001; Himanshu Kaul; Amit Agarwal 001; Steven Hsu; Ram Krishnamurthy 001 (VLSI Circuits, 2018)

A 220-900mV 179Mcode/s 36pJ/code Canonical Huffman Encoder for DEFLATE Compression in 14nm CMOS. - Sudhir Satpathy; Vikram B. Suresh; Raghavan Kumar; Vinodh Gopal; James Guilford; Kirk Yap; Mark A. Anders 001; Himanshu Kaul; Amit Agarwal 001; Steven Hsu; Ram Krishnamurthy 001; Sanu Mathew (CICC, 2019)

A 225-950mV 1.5Tbps/W Whirlpool Hashing Accelerator for Secure Automotive Platforms in 14nm CMOS. - Vikram B. Suresh; Sudhir Satpathy; Raghavan Kumar; Mark A. Anders 001; Himanshu Kaul; Amit Agarwal 001; Steven Hsu; Ram Krishnamurthy 001; Sanu Mathew (CICC, 2019)

A Microwatt-Class Always-On Sensor Fusion Engine Featuring Ultra-Low-Power AOI Clocked Circuits in 14nm CMOS. - Steven Hsu; Amit Agarwal 001; Monodeep Kar; Mark A. Anders 001; Himanshu Kaul; Raghavan Kumar; Sudhir Satpathy; Vikram B. Suresh; Sanu Mathew; Ram Krishnamurthy 001; Vivek De (VLSI Circuits, 2019)

A 4900×m2 839Mbps Side-Channel Attack Resistant AES-128 in 14nm CMOS with Heterogeneous Sboxes, Linear Masked MixColumns and Dual-Rail Key Addition. - Raghavan Kumar; Vikram B. Suresh; Monodeep Kar; Sudhir Satpathy; Mark A. Anders 001; Himanshu Kaul; Amit Agarwal 001; Steven Hsu; Gregory K. Chen; Ram Krishnamurthy 001; Vivek De; Sanu Mathew (VLSI Circuits, 2019)

A 1.4GHz 20.5Gbps GZIP decompression accelerator in 14nm CMOS featuring dual-path out-of-order speculative Huffman decoder and multi-write enabled register file array. - Sudhir Satpathy; Vikram B. Suresh; Raghavan Kumar; Vinodh Gopal; James Guilford; Mark A. Anders 001; Himanshu Kaul; Amit Agarwal 001; Steven Hsu; Ram Krishnamurthy 001; Vivek De; Sanu Mathew (VLSI Circuits, 2019)

A 250Mv, 0.063J/Ghash Bitcoin Mining Engine in 14nm CMOS Featuring Dual-Vcc Sha256 Datapath and 3-Phase Latch Based Clocking. - Vikram B. Suresh; Sudhir Satpathy; Raghavan Kumar; Mark A. Anders 001; Himanshu Kaul; Amit Agarwal 001; Steven Hsu; Ram Krishnamurthy 001; Vivek De; Sanu Mathew (VLSI Circuits, 2019)

An All-Digital Unified Physically Unclonable Function and True Random Number Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction in 14-nm Tri-gate CMOS. - Sudhir Satpathy; Sanu K. Mathew; Raghavan Kumar; Vikram B. Suresh; Mark A. Anders 001; Himanshu Kaul; Amit Agarwal 001; Steven Hsu; Ram K. Krishnamurthy; Vivek De (IEEE J. Solid State Circuits, 2019)

A 435MHz, 2.5Mbps/W Side-Channel-Attack Resistant Crypto-Processor for Secure RSA-4K Public-Key Encryption in 14nm CMOS. - Raghavan Kumar; Sudhir Satpathy; Vikram B. Suresh; Mark A. Anders 001; Himanshu Kaul; Vivek De; Sanu Mathew (VLSI Circuits, 2020)

A 4900- $ mu$ m2 839-Mb/s Side-Channel Attack- Resistant AES-128 in 14-nm CMOS With Heterogeneous Sboxes, Linear Masked MixColumns, and Dual-Rail Key Addition. - Raghavan Kumar; Vikram B. Suresh; Monodeep Kar; Sudhir Satpathy; Mark A. Anders 001; Himanshu Kaul; Amit Agarwal 001; Steven Hsu; Gregory K. Chen; Ram K. Krishnamurthy; Vivek De; Sanu K. Mathew (IEEE J. Solid State Circuits, 2020)

A Time-/Frequency-Domain Side-Channel Attack Resistant AES-128 and RSA-4K Crypto-Processor in 14-nm CMOS. - Raghavan Kumar; Xiaosen Liu; Vikram B. Suresh; Harish K. Krishnamurthy; Sudhir Satpathy; Mark A. Anders 001; Himanshu Kaul; Krishnan Ravichandran; Vivek De; Sanu K. Mathew (IEEE J. Solid State Circuits, 2021)