Sudipta Chattopadhyay

According to our database1, Sudipta Chattopadhyay authored at least 54 papers between 2009 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2020
An exploration of effective fuzzing for side-channel cache leakage.
Softw. Test. Verification Reliab., 2020

Genetic algorithm based estimation of non-functional properties for GPGPU programs.
J. Syst. Archit., 2020

STITCHER: Correlating Digital Forensic Evidence on Internet-of-Things Devices.
CoRR, 2020

Securing Autonomous Service Robots through Fuzzing, Detection, and Mitigation.
CoRR, 2020

Exposing Backdoors in Robust Machine Learning Models.
CoRR, 2020

Systematic Classification of Attackers via Bounded Model Checking.
Proceedings of the Verification, Model Checking, and Abstract Interpretation, 2020

2019
Compositional Design of Multi-Robot Systems Control Software on ROS.
ACM Trans. Embedded Comput. Syst., 2019

Quantifying the Information Leakage in Cache Attacks via Symbolic Execution.
ACM Trans. Embedded Comput. Syst., 2019

Circ-Tree: A B+-Tree Variant with Circular Design for Persistent Memory.
CoRR, 2019

Callisto: Entropy based test generation and data quality assessment for Machine Learning Systems.
CoRR, 2019

KLEESPECTRE: Detecting Information Leakage through Speculative Cache Attacks via Symbolic Execution.
CoRR, 2019

Model Agnostic Defence against Backdoor Attacks in Machine Learning.
CoRR, 2019

Grammar Based Directed Testing of Machine Learning Systems.
CoRR, 2019

Crash recoverable ARMv8-oriented B+-tree for byte-addressable persistent memory.
Proceedings of the 20th ACM SIGPLAN/SIGBED International Conference on Languages, 2019

Road Context-Aware Intrusion Detection System for Autonomous Cars.
Proceedings of the Information and Communications Security - 21st International Conference, 2019

Cache-Aware Kernel Tiling: An Approach for System-Level Performance Optimization of GPU-Based Applications.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
Symbolic Verification of Cache Side-Channel Freedom.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Taming the War in Memory: A Resilient Mitigation Strategy Against Memory Safety Attacks in CPS.
CoRR, 2018

oo7: Low-overhead Defense against Spectre Attacks via Binary Analysis.
CoRR, 2018

Wo ist der Fehler und wie wird er behoben? Ein Experiment mit Softwareentwicklern.
Proceedings of the Software Engineering und Software Management 2018, 2018

Automated directed fairness testing.
Proceedings of the 33rd ACM/IEEE International Conference on Automated Software Engineering, 2018

Enforcing Full-Stack Memory-Safety in Cyber-Physical Systems.
Proceedings of the Engineering Secure Software and Systems - 10th International Symposium, 2018

Road context-aware intrusion detection system for autonomous cars: work-in-progress.
Proceedings of the International Conference on Embedded Software, 2018

Measurement Based Execution Time Analysis of GPGPU Programs via SE+GA.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

LAWN: boosting the performance of NVMM file system through reducing write amplification.
Proceedings of the 55th Annual Design Automation Conference, 2018

Introducing assume-guarantee contracts for verifying robotic applications: work-in-progress.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2018

2017
Directed Automated Memory Performance Testing.
Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2017

Where is the bug and how is it fixed? an experiment with practitioners.
Proceedings of the 2017 11th Joint Meeting on Foundations of Software Engineering, 2017

Quantifying the information leak in cache attacks via symbolic execution.
Proceedings of the 15th ACM-IEEE International Conference on Formal Methods and Models for System Design, 2017

Testing Cache Side-Channel Leakage.
Proceedings of the 2017 IEEE International Conference on Software Testing, 2017

How developers debug software the DbgBench dataset: poster.
Proceedings of the 39th International Conference on Software Engineering, 2017

2016
Systematic detection of memory related performance bottlenecks in GPGPU programs.
J. Syst. Archit., 2016

Quantifying the Information Leak in Cache Attacks through Symbolic Execution.
CoRR, 2016

On Testing Embedded Software.
Adv. Comput., 2016

SPARTA: A scheduling policy for thwarting differential power analysis attacks.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
MESS: Memory Performance Debugging on Embedded Multi-core Systems.
Proceedings of the Model Checking Software - 22nd International Symposium, 2015

2014
Cache-Related Preemption Delay Analysis for Multilevel Noninclusive Caches.
ACM Trans. Embedded Comput. Syst., 2014

A Unified WCET analysis framework for multicore platforms.
ACM Trans. Embedded Comput. Syst., 2014

Static analysis of multi-core TDMA resource arbitration delays.
Real-Time Systems, 2014

Time-Predictable Embedded Software on Multi-Core Platforms: Analysis and Optimization.
Foundations and Trends in Electronic Design Automation, 2014

Detecting energy bugs and hotspots in mobile apps.
Proceedings of the 22nd ACM SIGSOFT International Symposium on Foundations of Software Engineering, (FSE-22), Hong Kong, China, November 16, 2014

Automated software testing of memory performance in embedded GPUs.
Proceedings of the 2014 International Conference on Embedded Software, 2014

2013
Scalable and precise refinement of cache timing analysis via path-sensitive verification.
Real-Time Systems, 2013

Integrated Timing Analysis of Application and Operating Systems Code.
Proceedings of the IEEE 34th Real-Time Systems Symposium, 2013

Static Analysis Driven Cache Performance Testing.
Proceedings of the IEEE 34th Real-Time Systems Symposium, 2013

Precise micro-architectural modeling for WCET analysis via AI+SAT.
Proceedings of the 19th IEEE Real-Time and Embedded Technology and Applications Symposium, 2013

Program performance spectrum.
Proceedings of the SIGPLAN/SIGBED Conference on Languages, 2013

2012
A Unified WCET Analysis Framework for Multi-core Platforms.
Proceedings of the 2012 IEEE 18th Real Time and Embedded Technology and Applications Symposium, 2012

2011
Scalable and Precise Refinement of Cache Timing Analysis via Model Checking.
Proceedings of the 32nd IEEE Real-Time Systems Symposium, 2011

Timing Analysis of a Protected Operating System Kernel.
Proceedings of the 32nd IEEE Real-Time Systems Symposium, 2011

Static bus schedule aware scratchpad allocation in multiprocessors.
Proceedings of the ACM SIGPLAN/SIGBED 2011 conference on Languages, 2011

Bus-Aware Multicore WCET Analysis through TDMA Offset Bounds.
Proceedings of the 23rd Euromicro Conference on Real-Time Systems, 2011

2010
Modeling shared cache and bus in multi-cores for timing analysis.
Proceedings of the 13th International Workshop on Software and Compilers for Embedded Systems, 2010

2009
Unified Cache Modeling for WCET Analysis and Layout Optimizations.
Proceedings of the 30th IEEE Real-Time Systems Symposium, 2009


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