Flare reduction in EUV Lithography by perturbation of wire segments. - Sudipta Paul 001; Pritha Banerjee 001; Susmita Sur-Kolay (VLSI-SoC, 2015)

Post-Layout Perturbation towards Stitch Friendly Layout for Multiple E-Beam Lithography. - Sudipta Paul 001; Pritha Banerjee 001; Susmita Sur-Kolay (ICCD, 2017)

Minimization of Flare in EUVL by Simultaneous Wire Segment Perturbation and Dummification. - Sudipta Paul 001; Pritha Banerjee 001; Susmita Sur-Kolay (ISVLSI, 2019)

A study on flare minimisation in EUV lithography by post-layout re-allocation of wire segments. - Sudipta Paul 001; Pritha Banerjee 001; Susmita Sur-Kolay (IET Circuits Devices Syst., 2021)

Stitch-avoiding Global Routing for Multiple E-Beam Lithography. - Kritanta Saha; Sudipta Paul 001; Pritha Banerjee 001; Susmita Sur-Kolay (VLSID, 2022)

Concurrent Steiner Tree Selection for Global routing with EUVL Flare Reduction. - Sudipta Paul 001; Tridib Mukherjee; Pritha Banerjee 001; Susmita Sur-Kolay (Integr., 2023)