PERI: A Posit Enabled RISC-V Core. - Sugandha Tiwari; Neel Gala; Chester Rebeiro; V. Kamakoti 001 (CoRR, 2019)

PERI: A Configurable Posit Enabled RISC-V Core. - Sugandha Tiwari; Neel Gala; Chester Rebeiro; V. Kamakoti 001 (ACM Trans. Archit. Code Optim., 2021)