SPAR-2: A SIMD Processor Array for Machine Learning in IoT Devices. - Suhail Basalama; Atiyehsadat Panahi; Ange-Thierry Ishimwe; David Andrews 001 (ICDIS, 2020)

A Customizable Domain-Specific Memory-Centric FPGA Overlay for Machine Learning Applications. - Atiyehsadat Panahi; Suhail Basalama; Ange-Thierry Ishimwe; Joel Mandebi Mbongue; David Andrews 001 (FPL, 2021)

A Versatile Systolic Array for Transposed and Dilated Convolution on FPGA. - Suhail Basalama; Atefeh Sohrabizadeh; Jie Wang 022; Jason Cong (FCCM, 2022)

A Comprehensive Automated Exploration Framework for Systolic Array Designs. - Suhail Basalama; Jie Wang 022; Jason Cong (DAC, 2023)

Callipepla: Stream Centric Instruction Set and Mixed Precision for Accelerating Conjugate Gradient Solver. - Linghao Song; Licheng Guo; Suhail Basalama; Yuze Chi; Robert F. Lucas; Jason Cong (FPGA, 2023)

FlexCNN: An End-to-end Framework for Composing CNN Accelerators on FPGA. - Suhail Basalama; Atefeh Sohrabizadeh; Jie Wang 022; Licheng Guo; Jason Cong (ACM Trans. Reconfigurable Technol. Syst., 2023)

TAPA-CS: Enabling Scalable Accelerator Design on Distributed HBM-FPGAs. - Neha Prakriya; Yuze Chi; Suhail Basalama; Linghao Song; Jason Cong (ASPLOS (3), 2024)

NoH: NoC Compilation in High-Level Synthesis. - Huifeng Ke; Sihao Liu; Licheng Guo; Zifan He; Linghao Song; Suhail Basalama; Yuze Chi; Tony Nowatzki; Jason Cong (FCCM, 2025)

Stream-HLS: Towards Automatic Dataflow Acceleration. - Suhail Basalama; Jason Cong (FPGA, 2025)